verilator/test_regress/t/t_interface_virtual.out
2023-10-16 11:05:39 -04:00

12 lines
339 B
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va==vb? 1
va!=vb? 0
va==vb? 0
va!=vb? 1
va.addr=aa va.data=11 ia.addr=aa ia.data=11
vb.addr=bb vb.data=22 ib.addr=bb ib.data=22
ca.fa.addr=a0 ca.fa.data=11 ca.fa.addr=b0 ca.fb.data=22
cb.fa.addr=b0 cb.fa.data=22 cb.fa.addr=a0 cb.fb.data=11
gen.x[0].addr=a0 gen.x[1].addr=b0
gen='{x:'{top.t.ia, top.t.ib, null, null} }
*-* All Finished *-*