mirror of
https://github.com/verilator/verilator.git
synced 2025-01-01 04:07:34 +00:00
Fix interface comparison (#4570)
This commit is contained in:
parent
ad3bcbb1bb
commit
bc9ff6d1bf
@ -6681,7 +6681,8 @@ private:
|
||||
// child node's width to end up correct for the assignment (etc)
|
||||
widthCheckSized(nodep, side, VN_AS(underp, NodeExpr), expDTypep, extendRule,
|
||||
warnOn);
|
||||
} else if (!VN_IS(expDTypep->skipRefp(), IfaceRefDType)
|
||||
} else if (!VN_IS(nodep, Eq) && !VN_IS(nodep, Neq)
|
||||
&& !VN_IS(expDTypep->skipRefp(), IfaceRefDType)
|
||||
&& VN_IS(underp->dtypep()->skipRefp(), IfaceRefDType)) {
|
||||
underp->v3error(ucfirst(nodep->prettyOperatorName())
|
||||
<< " expected non-interface on " << side << " but "
|
||||
|
@ -1,3 +1,7 @@
|
||||
va==vb? 1
|
||||
va!=vb? 0
|
||||
va==vb? 0
|
||||
va!=vb? 1
|
||||
va.addr=aa va.data=11 ia.addr=aa ia.data=11
|
||||
vb.addr=bb vb.data=22 ib.addr=bb ib.data=22
|
||||
ca.fa.addr=a0 ca.fa.data=11 ca.fa.addr=b0 ca.fb.data=22
|
||||
|
@ -33,7 +33,12 @@ module t (/*AUTOARG*/);
|
||||
|
||||
initial begin
|
||||
va = ia;
|
||||
vb = ia;
|
||||
$display("va==vb? %b", va==vb);
|
||||
$display("va!=vb? %b", va!=vb);
|
||||
vb = ib;
|
||||
$display("va==vb? %b", va==vb);
|
||||
$display("va!=vb? %b", va!=vb);
|
||||
|
||||
ca = new;
|
||||
cb = new;
|
||||
|
Loading…
Reference in New Issue
Block a user