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126 lines
3.7 KiB
Systemverilog
126 lines
3.7 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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typedef bit signed [11:0] s12_t;
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typedef bit unsigned [11:0] u12_t;
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typedef bit signed [69:0] s70_t;
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typedef bit unsigned [69:0] u70_t;
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import "DPI-C" context function void dpii_inv_s12(input s12_t in, output s12_t out);
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import "DPI-C" context function void dpii_inv_u12(input u12_t in, output u12_t out);
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import "DPI-C" context function void dpii_inv_s70(input s70_t in, output s70_t out);
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import "DPI-C" context function void dpii_inv_u70(input s70_t in, output u70_t out);
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class Cls #(type T = bit);
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static function void get(inout T value);
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`ifdef TEST_NOINLINE
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// verilator no_inline_task
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`endif
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value = ~value;
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endfunction
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endclass
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module t;
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parameter MSG_PORT_WIDTH = 4350;
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localparam PAYLOAD_MAX_BITS = 4352;
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reg [MSG_PORT_WIDTH-1:0] msg;
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function void func (output bit [PAYLOAD_MAX_BITS-1:0] data);
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`ifdef TEST_NOINLINE
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// verilator no_inline_task
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`endif
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data = {PAYLOAD_MAX_BITS{1'b1}};
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endfunction
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s12_t ds12;
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u12_t du12;
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s70_t ds70;
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u70_t du70;
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s12_t qs12;
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u12_t qu12;
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s70_t qs70;
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u70_t qu70;
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initial begin
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// Operator TASKREF 'func' expects 4352 bits on the Function Argument, but Function Argument's VARREF 'msg' generates 4350 bits.
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// verilator lint_off WIDTHEXPAND
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func(msg);
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if (msg !== {MSG_PORT_WIDTH{1'b1}}) $stop;
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begin
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// narrow connect to wide
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ds12 = 12'h234;
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Cls#(s70_t)::get(ds12);
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`checkh(ds12, 12'hdcb);
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ds12 = 12'he34; // negative if signed
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Cls#(s70_t)::get(ds12);
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`checkh(ds12, 12'h1cb);
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du12 = 12'h244;
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Cls#(u70_t)::get(du12);
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`checkh(du12, 12'hdbb);
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du12 = 12'he34; // negative if signed
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Cls#(u70_t)::get(du12);
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`checkh(du12, 12'h1cb);
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// wie connect to narrow
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ds70 = 12'h254;
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Cls#(s12_t)::get(ds70);
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`checkh(ds70, 70'h3ffffffffffffffdab);
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ds70 = 12'he34; // negative if signed
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Cls#(s12_t)::get(ds70);
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`checkh(ds70, 70'h0000000000000001cb);
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du70 = 12'h264;
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Cls#(u12_t)::get(du70);
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`checkh(du70, 70'h000000000000000d9b);
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du70 = 12'he34; // negative if signed
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Cls#(u12_t)::get(du70);
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`checkh(du70, 70'h0000000000000001cb);
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end
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begin
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// narrow connect to wide
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ds12 = 12'h234;
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dpii_inv_s70(ds12, qs12);
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`checkh(qs12, 12'hdcb);
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ds12 = 12'he34; // negative if signed
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dpii_inv_s70(ds12, qs12);
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`checkh(qs12, 12'h1cb);
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du12 = 12'h244;
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dpii_inv_u70(du12, qu12);
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`checkh(qu12, 12'hdbb);
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du12 = 12'he34; // negative if signed
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dpii_inv_u70(ds12, qs12);
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`checkh(qs12, 12'h1cb);
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// wie connect to narrow
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ds70 = 12'h254;
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dpii_inv_s12(ds70, qs70);
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`checkh(qs70, 70'h3ffffffffffffffdab);
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ds70 = 12'he34; // negative if signed
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dpii_inv_s12(ds70, qs70);
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`checkh(qs70, 70'h0000000000000001cb);
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du70 = 12'h264;
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dpii_inv_u12(du70, qu70);
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`checkh(qu70, 70'h000000000000000d9b);
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du70 = 12'he34; // negative if signed
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dpii_inv_u12(du70, qu70);
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`checkh(qu70, 70'h0000000000000001cb);
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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