verilator/test_regress/t/t_disable_fork_notiming.v
2023-10-16 14:02:29 +02:00

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258 B
Systemverilog

// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2023 by Antmicro Ltd.
// SPDX-License-Identifier: CC0-1.0
module t;
initial disable fork;
endmodule