verilator/test_regress/t/t_disable_fork_notiming.v

10 lines
258 B
Systemverilog
Raw Normal View History

2023-10-16 12:02:29 +00:00
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2023 by Antmicro Ltd.
// SPDX-License-Identifier: CC0-1.0
module t;
initial disable fork;
endmodule