verilator/test_regress/t/t_assert_ctl_immediate_bad.pl
Bartłomiej Chmiel 2a9f29912c
Add parameterless assert control system tasks (#5010)
Signed-off-by: Bartłomiej Chmiel <bchmiel@antmicro.com>
Co-authored-by: Ryszard Rozak <rrozak@antmicro.com>
Co-authored-by: Wilson Snyder <wsnyder@wsnyder.org>
Co-authored-by: Arkadiusz Kozdra <akozdra@antmicro.com>
2024-05-08 08:31:34 -04:00

24 lines
676 B
Perl
Executable File

#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(vlt => 1);
compile(
verilator_flags2 => ['--assert', '--timing'],
);
execute(
all_run_flags => ["+verilator+error+limit+100"],
expect_filename => $Self->{golden_filename},
);
ok(1);
1;