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Add parameterless assert control system tasks (#5010)
Signed-off-by: Bartłomiej Chmiel <bchmiel@antmicro.com> Co-authored-by: Ryszard Rozak <rrozak@antmicro.com> Co-authored-by: Wilson Snyder <wsnyder@wsnyder.org> Co-authored-by: Arkadiusz Kozdra <akozdra@antmicro.com>
This commit is contained in:
Bartłomiej Chmiel
GitHub
parent
298e0f24d1
commit
2a9f29912c
@ -518,6 +518,54 @@ class AssertVisitor final : public VNVisitor {
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iterateChildren(nodep);
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newPslAssertion(nodep, nodep->failsp());
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}
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void visit(AstAssertCtl* nodep) override {
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if (VN_IS(m_modp, Class) || VN_IS(m_modp, Iface)) {
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nodep->v3warn(E_UNSUPPORTED, "Unsupported: assertcontrols in classes or interfaces");
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VL_DO_DANGLING(pushDeletep(nodep->unlinkFrBack()), nodep);
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return;
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}
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iterateChildren(nodep);
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if (const AstConst* const constp = VN_CAST(nodep->controlTypep(), Const)) {
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nodep->ctlType(constp->toSInt());
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} else if (nodep->ctlType() == VAssertCtlType::_TO_BE_EVALUATED) {
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nodep->v3warn(E_UNSUPPORTED, "Unsupported: non-const assert control type expression");
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VL_DO_DANGLING(pushDeletep(nodep->unlinkFrBack()), nodep);
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return;
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}
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switch (nodep->ctlType()) {
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case VAssertCtlType::ON:
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case VAssertCtlType::OFF:
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case VAssertCtlType::KILL: {
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UINFO(9, "Generating assertctl for a module: " << m_modp << endl);
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FileLine* const fl = nodep->fileline();
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const string assertOnStmt
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= string{"vlSymsp->_vm_contextp__->assertOn("}
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+ (nodep->ctlType() == VAssertCtlType::ON ? "true" : "false") + ");\n";
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nodep->replaceWith(new AstCExpr{fl, assertOnStmt, 1});
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break;
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}
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case VAssertCtlType::LOCK:
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case VAssertCtlType::UNLOCK:
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case VAssertCtlType::PASS_ON:
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case VAssertCtlType::PASS_OFF:
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case VAssertCtlType::FAIL_ON:
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case VAssertCtlType::FAIL_OFF:
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case VAssertCtlType::NONVACUOUS_ON:
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case VAssertCtlType::VACUOUS_OFF: {
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nodep->unlinkFrBack();
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nodep->v3warn(E_UNSUPPORTED, "Unsupported assertcontrol control_type");
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break;
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}
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default: {
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nodep->unlinkFrBack();
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nodep->v3warn(EC_ERROR, "Bad assertcontrol control_type (IEEE 1800-2023 Table 20-5)");
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}
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}
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VL_DO_DANGLING(pushDeletep(nodep), nodep);
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}
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void visit(AstAssertIntrinsic* nodep) override {
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iterateChildren(nodep);
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newPslAssertion(nodep, nodep->failsp());
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55
src/V3Ast.h
55
src/V3Ast.h
@ -1102,6 +1102,61 @@ constexpr bool operator==(VAlwaysKwd::en lhs, const VAlwaysKwd& rhs) { return lh
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// ######################################################################
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class VAssertCtlType final {
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public:
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// IEEE 1800-2023 Table 20-5
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enum en : uint8_t {
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_TO_BE_EVALUATED = 0,
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LOCK = 1,
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UNLOCK = 2,
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ON = 3,
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OFF = 4,
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KILL = 5,
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PASS_ON = 6,
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PASS_OFF = 7,
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FAIL_ON = 8,
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FAIL_OFF = 9,
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NONVACUOUS_ON = 10,
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VACUOUS_OFF = 11
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};
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enum en m_e;
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VAssertCtlType()
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: m_e{_TO_BE_EVALUATED} {}
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// cppcheck-suppress noExplicitConstructor
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constexpr VAssertCtlType(en _e)
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: m_e{_e} {}
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explicit VAssertCtlType(int _e)
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: m_e(static_cast<en>(_e)) {} // Need () or GCC 4.8 false warning
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constexpr operator en() const { return m_e; }
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const char* ascii() const {
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// IEEE 1800-2023 20.11
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static const char* const names[] = {"",
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"",
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"",
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"$asserton",
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"$assertoff",
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"$assertkill",
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"$assertpasson",
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"$assertpassoff",
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"$assertfailon",
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"$assertfailoff",
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"$assertnonvacuouson",
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"$assertvacuousoff"};
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return names[m_e];
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}
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};
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constexpr bool operator==(const VAssertCtlType& lhs, const VAssertCtlType& rhs) {
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return lhs.m_e == rhs.m_e;
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}
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constexpr bool operator==(const VAssertCtlType& lhs, VAssertCtlType::en rhs) {
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return lhs.m_e == rhs;
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}
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constexpr bool operator==(VAssertCtlType::en lhs, const VAssertCtlType& rhs) {
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return lhs == rhs.m_e;
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}
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// ######################################################################
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class VCaseType final {
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public:
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enum en : uint8_t { CT_CASE, CT_CASEX, CT_CASEZ, CT_CASEINSIDE };
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@ -2578,6 +2578,31 @@ public:
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bool isJustOneBodyStmt() const { return stmtsp() && !stmtsp()->nextp(); }
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bool isFirstInMyListOfStatements(AstNode* n) const override { return n == stmtsp(); }
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};
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class AstAssertCtl final : public AstNodeStmt {
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// @astgen op1 := controlTypep : AstNodeExpr
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// @astgen op2 := levelp : AstNodeExpr
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// @astgen op3 := itemsp : List[AstNodeExpr]
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// Type of assertcontrol task; either known from parser or from evaluated
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// controlTypep expression.
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VAssertCtlType m_ctlType; // $assert keyword type
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public:
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AstAssertCtl(FileLine* fl, VAssertCtlType ctlType, AstNodeExpr* levelp = nullptr,
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AstNodeExpr* itemsp = nullptr);
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AstAssertCtl(FileLine* fl, AstNodeExpr* controlTypep, AstNodeExpr* assertionTypep = nullptr,
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AstNodeExpr* directiveTypep = nullptr, AstNodeExpr* levelp = nullptr,
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AstNodeExpr* itemsp = nullptr);
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ASTGEN_MEMBERS_AstAssertCtl;
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string verilogKwd() const override { return m_ctlType.ascii(); }
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bool isGateOptimizable() const override { return false; }
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bool isPredictOptimizable() const override { return false; }
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bool isPure() override { return false; }
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bool isOutputter() override { return true; }
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VAssertCtlType ctlType() const { return m_ctlType; }
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void ctlType(int32_t type) { m_ctlType = VAssertCtlType{type}; }
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void dump(std::ostream& str = std::cout) const override;
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void dumpJson(std::ostream& str = std::cout) const override;
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};
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class AstBreak final : public AstNodeStmt {
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public:
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explicit AstBreak(FileLine* fl)
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@ -1458,7 +1458,32 @@ void AstAlways::dumpJson(std::ostream& str) const {
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dumpJsonStr(str, "keyword", keyword().ascii());
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dumpJsonGen(str);
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}
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AstAssertCtl::AstAssertCtl(FileLine* fl, VAssertCtlType ctlType, AstNodeExpr* levelp,
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AstNodeExpr* itemsp)
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: ASTGEN_SUPER_AssertCtl(fl)
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, m_ctlType{ctlType} {
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controlTypep(new AstConst{fl, ctlType});
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if (!levelp) levelp = new AstConst{fl, 0};
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this->levelp(levelp);
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addItemsp(itemsp);
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}
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AstAssertCtl::AstAssertCtl(FileLine* fl, AstNodeExpr* controlTypep, AstNodeExpr*, AstNodeExpr*,
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AstNodeExpr* levelp, AstNodeExpr* itemsp)
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: ASTGEN_SUPER_AssertCtl(fl)
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, m_ctlType{VAssertCtlType::_TO_BE_EVALUATED} {
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this->controlTypep(controlTypep);
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if (!levelp) levelp = new AstConst{fl, 0};
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this->levelp(levelp);
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addItemsp(itemsp);
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}
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void AstAssertCtl::dump(std::ostream& str) const {
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this->AstNode::dump(str);
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str << " [" << ctlType().ascii() << "]";
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}
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void AstAssertCtl::dumpJson(std::ostream& str) const {
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dumpJsonStr(str, "ctlType", ctlType().ascii());
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dumpJsonGen(str);
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}
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void AstAttrOf::dump(std::ostream& str) const {
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this->AstNode::dump(str);
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str << " [" << attrType().ascii() << "]";
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@ -84,6 +84,7 @@ class EmitCConstPool final : public EmitCConstInit {
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putns(varp, "extern const ");
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putns(varp, varp->dtypep()->cType(nameProtect, false, false));
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putns(varp, " = ");
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UASSERT_OBJ(varp, varp->valuep(), "Var without value");
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iterateConst(varp->valuep());
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putns(varp, ";\n");
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// Keep track of stats
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@ -618,6 +618,11 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
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/* System Verilog 2012 */
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<S12,S17,S23,SAX>{
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/* System Tasks */
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"$assertcontrol" { FL; return yD_ASSERTCTL; }
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"$assertkill" { FL; return yD_ASSERTKILL; }
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"$assertoff" { FL; return yD_ASSERTOFF; }
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"$asserton" { FL; return yD_ASSERTON; }
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/* Keywords */
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"implements" { FL; return yIMPLEMENTS; }
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"interconnect" { FL; return yINTERCONNECT; }
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@ -807,6 +807,10 @@ BISONPRE_VERSION(3.7,%define api.header.include {"V3ParseBison.h"})
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%token<fl> yD_ACOSH "$acosh"
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%token<fl> yD_ASIN "$asin"
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%token<fl> yD_ASINH "$asinh"
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%token<fl> yD_ASSERTCTL "$assertcontrol"
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%token<fl> yD_ASSERTKILL "$assertkill"
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%token<fl> yD_ASSERTOFF "$assertoff"
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%token<fl> yD_ASSERTON "$asserton"
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%token<fl> yD_ATAN "$atan"
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%token<fl> yD_ATAN2 "$atan2"
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%token<fl> yD_ATANH "$atanh"
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@ -4224,6 +4228,21 @@ system_t_call<nodeStmtp>: // IEEE: system_tf_call (as task)
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{ $$ = new AstDisplay{$1, VDisplayType::DT_FATAL, nullptr, $5};
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$$->addNext(new AstStop{$1, false}); DEL($3); }
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//
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| yD_ASSERTCTL '(' expr ')' { $$ = new AstAssertCtl{$1, $3}; }
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| yD_ASSERTCTL '(' expr ',' exprE ')' { $$ = new AstAssertCtl{$1, $3, $5}; }
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| yD_ASSERTCTL '(' expr ',' exprE ',' exprE ')' { $$ = new AstAssertCtl{$1, $3, $5, $7}; }
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| yD_ASSERTCTL '(' expr ',' exprE ',' exprE ',' exprE ')' { $$ = new AstAssertCtl{$1, $3, $5, $7, $9}; }
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| yD_ASSERTCTL '(' expr ',' exprE ',' exprE ',' exprE ',' exprList ')' { $$ = new AstAssertCtl{$1, $3, $5, $7, $9, $11}; }
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| yD_ASSERTKILL parenE { $$ = new AstAssertCtl{$1, VAssertCtlType::KILL}; }
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| yD_ASSERTKILL '(' expr ')' { $$ = new AstAssertCtl{$1, VAssertCtlType::KILL, $3}; }
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| yD_ASSERTKILL '(' exprE ',' exprList ')' { $$ = new AstAssertCtl{$1, VAssertCtlType::KILL, $3, $5}; }
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| yD_ASSERTOFF parenE { $$ = new AstAssertCtl{$1, VAssertCtlType::OFF}; }
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| yD_ASSERTOFF '(' expr ')' { $$ = new AstAssertCtl{$1, VAssertCtlType::OFF, $3}; }
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| yD_ASSERTOFF '(' exprE ',' exprList ')' { $$ = new AstAssertCtl{$1, VAssertCtlType::OFF, $3, $5}; }
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| yD_ASSERTON parenE { $$ = new AstAssertCtl{$1, VAssertCtlType::ON}; }
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| yD_ASSERTON '(' expr ')' { $$ = new AstAssertCtl{$1, VAssertCtlType::ON, $3}; }
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| yD_ASSERTON '(' exprE ',' exprList ')' { $$ = new AstAssertCtl{$1, VAssertCtlType::ON, $3, $5}; }
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//
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| yD_MONITOROFF parenE { $$ = new AstMonitorOff{$1, true}; }
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| yD_MONITORON parenE { $$ = new AstMonitorOff{$1, false}; }
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//
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@ -4799,7 +4818,7 @@ constExpr<nodeExprp>:
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expr { $$ = $1; }
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;
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exprE<nodep>: // IEEE: optional expression
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exprE<nodeExprp>: // IEEE: optional expression
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/*empty*/ { $$ = nullptr; }
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| expr { $$ = $1; }
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;
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22
test_regress/t/t_assert_ctl_concurrent.pl
Executable file
22
test_regress/t/t_assert_ctl_concurrent.pl
Executable file
@ -0,0 +1,22 @@
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2024 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(vlt => 1);
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compile(
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verilator_flags2 => ["--exe --main --timing --assert"],
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);
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execute(
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check_finished => 1,
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);
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ok(1);
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1;
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44
test_regress/t/t_assert_ctl_concurrent.v
Normal file
44
test_regress/t/t_assert_ctl_concurrent.v
Normal file
@ -0,0 +1,44 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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bit clock = 1'b0;
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bit reset = 1'b0;
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initial begin
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$assertkill;
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#10
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reset = 1'b1;
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$display("%t: deassert reset %d", $time, reset);
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#40
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$asserton;
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reset = 1'b0;
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$display("%t: deassert reset %d", $time, reset);
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#200
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$display("%t: finish", $time);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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always #10 clock = ~clock;
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reg r = 1'b0;
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always @(posedge clock) if (reset) r <= 1'b1;
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assert_test:
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assert property (@(posedge clock) (reset | r))
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else $error("%t: assertion triggered", $time);
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endmodule
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23
test_regress/t/t_assert_ctl_concurrent_noinl.pl
Executable file
23
test_regress/t/t_assert_ctl_concurrent_noinl.pl
Executable file
@ -0,0 +1,23 @@
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2024 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
|
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# Lesser General Public License Version 3 or the Perl Artistic License
|
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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top_filename("t_assert_ctl_concurrent.v");
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scenarios(vlt => 1);
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compile(
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verilator_flags2 => ["--exe --main --timing --assert --fno-inline"],
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);
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execute(
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check_finished => 1,
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);
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ok(1);
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1;
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10
test_regress/t/t_assert_ctl_immediate_bad.out
Normal file
10
test_regress/t/t_assert_ctl_immediate_bad.out
Normal file
@ -0,0 +1,10 @@
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[0] %Error: t_assert_ctl_immediate_bad.v:50: Assertion failed in top.t.module_with_assertctl: 'assert' failed.
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-Info: t/t_assert_ctl_immediate_bad.v:50: Verilog $stop, ignored due to +verilator+error+limit
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[0] %Error: t_assert_ctl_immediate_bad.v:54: Assertion failed in top.t.module_with_assertctl: 'assert' failed.
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[0] %Error: t_assert_ctl_immediate_bad.v:59: Assertion failed in top.t.module_with_assertctl: 'assert' failed.
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[0] %Error: t_assert_ctl_immediate_bad.v:63: Assertion failed in top.t.module_with_assertctl: 'assert' failed.
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[0] %Error: t_assert_ctl_immediate_bad.v:68: Assertion failed in top.t.module_with_assertctl: 'assert' failed.
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[0] %Error: t_assert_ctl_immediate_bad.v:74: Assertion failed in top.t.module_with_assertctl: 'assert' failed.
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[0] %Error: t_assert_ctl_immediate_bad.v:45: Assertion failed in top.t.module_with_assertctl.f_assert: 'assert' failed.
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[0] %Error: t_assert_ctl_immediate_bad.v:45: Assertion failed in top.t.module_with_assertctl.f_assert: 'assert' failed.
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*-* All Finished *-*
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23
test_regress/t/t_assert_ctl_immediate_bad.pl
Executable file
23
test_regress/t/t_assert_ctl_immediate_bad.pl
Executable file
@ -0,0 +1,23 @@
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
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#
|
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# Copyright 2024 by Wilson Snyder. This program is free software; you
|
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# can redistribute it and/or modify it under the terms of either the GNU
|
||||
# Lesser General Public License Version 3 or the Perl Artistic License
|
||||
# Version 2.0.
|
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(vlt => 1);
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compile(
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verilator_flags2 => ['--assert', '--timing'],
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);
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execute(
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all_run_flags => ["+verilator+error+limit+100"],
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expect_filename => $Self->{golden_filename},
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);
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ok(1);
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1;
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||||
82
test_regress/t/t_assert_ctl_immediate_bad.v
Normal file
82
test_regress/t/t_assert_ctl_immediate_bad.v
Normal file
@ -0,0 +1,82 @@
|
||||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2024 by Antmicro.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
|
||||
input clk;
|
||||
|
||||
module_with_assert module_with_assert(clk);
|
||||
module_with_assertctl module_with_assertctl(clk);
|
||||
|
||||
always @ (posedge clk) begin
|
||||
assert(0);
|
||||
end
|
||||
|
||||
always @ (negedge clk) begin
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
endmodule
|
||||
|
||||
module module_with_assert(input clk);
|
||||
always @(posedge clk) assert(0);
|
||||
endmodule
|
||||
|
||||
module module_with_assertctl(input clk);
|
||||
let ON = 3;
|
||||
let OFF = 4;
|
||||
let KILL = 5;
|
||||
|
||||
function void assert_off; begin
|
||||
$assertoff;
|
||||
end
|
||||
endfunction
|
||||
function void assert_on; begin
|
||||
$asserton;
|
||||
end
|
||||
endfunction
|
||||
function void f_assert; begin
|
||||
assert(0);
|
||||
end
|
||||
endfunction
|
||||
|
||||
initial begin
|
||||
assert(0);
|
||||
$assertoff;
|
||||
assert(0);
|
||||
$asserton;
|
||||
assert(0);
|
||||
$assertkill;
|
||||
assert(0);
|
||||
|
||||
$assertcontrol(ON);
|
||||
assert(0);
|
||||
$assertcontrol(OFF);
|
||||
assert(0);
|
||||
$assertcontrol(ON);
|
||||
assert(0);
|
||||
$assertcontrol(KILL);
|
||||
assert(0);
|
||||
|
||||
assert_on();
|
||||
assert(0);
|
||||
assert_off();
|
||||
assert_off();
|
||||
assert(0);
|
||||
assert_on();
|
||||
assert_on();
|
||||
assert(0);
|
||||
|
||||
f_assert();
|
||||
f_assert();
|
||||
assert_off();
|
||||
f_assert();
|
||||
f_assert();
|
||||
end
|
||||
endmodule
|
||||
25
test_regress/t/t_assert_ctl_immediate_noinl_bad.pl
Executable file
25
test_regress/t/t_assert_ctl_immediate_noinl_bad.pl
Executable file
@ -0,0 +1,25 @@
|
||||
#!/usr/bin/env perl
|
||||
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
|
||||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||||
#
|
||||
# Copyright 2024 by Wilson Snyder. This program is free software; you
|
||||
# can redistribute it and/or modify it under the terms of either the GNU
|
||||
# Lesser General Public License Version 3 or the Perl Artistic License
|
||||
# Version 2.0.
|
||||
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
|
||||
|
||||
top_filename("t_assert_ctl_immediate_bad.v");
|
||||
golden_filename("t/t_assert_ctl_immediate_bad.out");
|
||||
scenarios(vlt => 1);
|
||||
|
||||
compile(
|
||||
verilator_flags2 => ['--assert --timing --fno-inline'],
|
||||
);
|
||||
|
||||
execute(
|
||||
all_run_flags => ["+verilator+error+limit+100"],
|
||||
expect_filename => $Self->{golden_filename},
|
||||
);
|
||||
|
||||
ok(1);
|
||||
1;
|
||||
56
test_regress/t/t_assert_ctl_unsup.out
Normal file
56
test_regress/t/t_assert_ctl_unsup.out
Normal file
@ -0,0 +1,56 @@
|
||||
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:18:7: Unsupported assertcontrol control_type
|
||||
18 | $assertcontrol(1);
|
||||
| ^~~~~~~~~~~~~~
|
||||
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
|
||||
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:19:7: Unsupported assertcontrol control_type
|
||||
19 | $assertcontrol(2);
|
||||
| ^~~~~~~~~~~~~~
|
||||
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:20:7: Unsupported assertcontrol control_type
|
||||
20 | $assertcontrol(6);
|
||||
| ^~~~~~~~~~~~~~
|
||||
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:21:7: Unsupported assertcontrol control_type
|
||||
21 | $assertcontrol(7);
|
||||
| ^~~~~~~~~~~~~~
|
||||
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:22:7: Unsupported assertcontrol control_type
|
||||
22 | $assertcontrol(8);
|
||||
| ^~~~~~~~~~~~~~
|
||||
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:23:7: Unsupported assertcontrol control_type
|
||||
23 | $assertcontrol(9);
|
||||
| ^~~~~~~~~~~~~~
|
||||
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:24:7: Unsupported assertcontrol control_type
|
||||
24 | $assertcontrol(10);
|
||||
| ^~~~~~~~~~~~~~
|
||||
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:25:7: Unsupported assertcontrol control_type
|
||||
25 | $assertcontrol(11);
|
||||
| ^~~~~~~~~~~~~~
|
||||
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:32:7: Unsupported: non-const assert control type expression
|
||||
: ... note: In instance 't.unsupported_ctl_type_expr'
|
||||
32 | $assertcontrol(ctl_type);
|
||||
| ^~~~~~~~~~~~~~
|
||||
%Error: t/t_assert_ctl_unsup.v:38:7: Bad assertcontrol control_type (IEEE 1800-2023 Table 20-5)
|
||||
38 | $assertcontrol(0);
|
||||
| ^~~~~~~~~~~~~~
|
||||
%Error: t/t_assert_ctl_unsup.v:39:7: Bad assertcontrol control_type (IEEE 1800-2023 Table 20-5)
|
||||
39 | $assertcontrol(100);
|
||||
| ^~~~~~~~~~~~~~
|
||||
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:68:10: Unsupported: assertcontrols in classes or interfaces
|
||||
: ... note: In instance 't.assert_class'
|
||||
68 | $asserton;
|
||||
| ^~~~~~~~~
|
||||
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:74:10: Unsupported: assertcontrols in classes or interfaces
|
||||
: ... note: In instance 't.assert_class'
|
||||
74 | $assertoff;
|
||||
| ^~~~~~~~~~
|
||||
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:147:7: Unsupported: assertcontrols in classes or interfaces
|
||||
: ... note: In instance 't.assert_iface'
|
||||
147 | $assertoff;
|
||||
| ^~~~~~~~~~
|
||||
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:113:7: Unsupported: assertcontrols in classes or interfaces
|
||||
: ... note: In instance 't.assert_iface_class'
|
||||
113 | $assertoff;
|
||||
| ^~~~~~~~~~
|
||||
%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:120:7: Unsupported: assertcontrols in classes or interfaces
|
||||
: ... note: In instance 't.assert_iface_class'
|
||||
120 | $asserton;
|
||||
| ^~~~~~~~~
|
||||
%Error: Exiting due to
|
||||
20
test_regress/t/t_assert_ctl_unsup.pl
Executable file
20
test_regress/t/t_assert_ctl_unsup.pl
Executable file
@ -0,0 +1,20 @@
|
||||
#!/usr/bin/env perl
|
||||
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
|
||||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||||
#
|
||||
# Copyright 2024 by Wilson Snyder. This program is free software; you
|
||||
# can redistribute it and/or modify it under the terms of either the GNU
|
||||
# Lesser General Public License Version 3 or the Perl Artistic License
|
||||
# Version 2.0.
|
||||
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
|
||||
|
||||
scenarios(linter => 1);
|
||||
|
||||
lint(
|
||||
verilator_flags2 => ['--assert'],
|
||||
fails => 1,
|
||||
expect_filename => $Self->{golden_filename},
|
||||
);
|
||||
|
||||
ok(1);
|
||||
1;
|
||||
160
test_regress/t/t_assert_ctl_unsup.v
Executable file
160
test_regress/t/t_assert_ctl_unsup.v
Executable file
@ -0,0 +1,160 @@
|
||||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2024 by Antmicro.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t;
|
||||
unsupported_ctl_type unsupported_ctl_type();
|
||||
unsupported_ctl_type_expr unsupported_ctl_type_expr();
|
||||
bad_assertcontrol_ctl_type bad_assertcontrol_ctl_type();
|
||||
assert_class assert_class();
|
||||
assert_iface assert_iface();
|
||||
assert_iface_class assert_iface_class();
|
||||
endmodule
|
||||
|
||||
module unsupported_ctl_type;
|
||||
initial begin
|
||||
$assertcontrol(1);
|
||||
$assertcontrol(2);
|
||||
$assertcontrol(6);
|
||||
$assertcontrol(7);
|
||||
$assertcontrol(8);
|
||||
$assertcontrol(9);
|
||||
$assertcontrol(10);
|
||||
$assertcontrol(11);
|
||||
end
|
||||
endmodule
|
||||
|
||||
module unsupported_ctl_type_expr;
|
||||
int ctl_type = 1;
|
||||
initial begin
|
||||
$assertcontrol(ctl_type);
|
||||
end
|
||||
endmodule
|
||||
|
||||
module bad_assertcontrol_ctl_type;
|
||||
initial begin
|
||||
$assertcontrol(0);
|
||||
$assertcontrol(100);
|
||||
end
|
||||
endmodule
|
||||
|
||||
module assert_class;
|
||||
virtual class AssertCtl;
|
||||
pure virtual function void virtual_assert_ctl();
|
||||
endclass
|
||||
|
||||
class AssertCls;
|
||||
static function void static_function();
|
||||
assert(0);
|
||||
endfunction
|
||||
static task static_task();
|
||||
assert(0);
|
||||
endtask
|
||||
function void assert_function();
|
||||
assert(0);
|
||||
endfunction
|
||||
task assert_task();
|
||||
assert(0);
|
||||
endtask
|
||||
virtual function void virtual_assert();
|
||||
assert(0);
|
||||
endfunction
|
||||
endclass
|
||||
|
||||
class AssertOn extends AssertCtl;
|
||||
virtual function void virtual_assert_ctl();
|
||||
$asserton;
|
||||
endfunction
|
||||
endclass
|
||||
|
||||
class AssertOff extends AssertCtl;
|
||||
virtual function void virtual_assert_ctl();
|
||||
$assertoff;
|
||||
endfunction
|
||||
endclass
|
||||
|
||||
AssertCls assertCls;
|
||||
AssertOn assertOn;
|
||||
AssertOff assertOff;
|
||||
initial begin
|
||||
$assertoff;
|
||||
AssertCls::static_function();
|
||||
AssertCls::static_task();
|
||||
$asserton;
|
||||
AssertCls::static_function();
|
||||
AssertCls::static_task();
|
||||
|
||||
assertCls = new;
|
||||
assertOn = new;
|
||||
assertOff = new;
|
||||
|
||||
assertOff.virtual_assert_ctl();
|
||||
assertCls.assert_function();
|
||||
assertCls.assert_task();
|
||||
assertCls.virtual_assert();
|
||||
|
||||
assertOn.virtual_assert_ctl();
|
||||
assertCls.assert_function();
|
||||
assertCls.assert_task();
|
||||
assertCls.virtual_assert();
|
||||
assertOff.virtual_assert_ctl();
|
||||
assertCls.assert_function();
|
||||
end
|
||||
endmodule
|
||||
|
||||
interface Iface;
|
||||
function void assert_func();
|
||||
assert(0);
|
||||
endfunction
|
||||
|
||||
function void assertoff_func();
|
||||
$assertoff;
|
||||
endfunction
|
||||
|
||||
initial begin
|
||||
assertoff_func();
|
||||
assert(0);
|
||||
assert_func();
|
||||
$asserton;
|
||||
assert(0);
|
||||
assert_func();
|
||||
end
|
||||
endinterface
|
||||
|
||||
module assert_iface;
|
||||
Iface iface();
|
||||
virtual Iface vIface = iface;
|
||||
initial begin
|
||||
vIface.assert_func();
|
||||
vIface.assertoff_func();
|
||||
vIface.assert_func();
|
||||
|
||||
iface.assert_func();
|
||||
iface.assertoff_func();
|
||||
iface.assert_func();
|
||||
end
|
||||
endmodule
|
||||
|
||||
interface class IfaceClass;
|
||||
pure virtual function void assertoff_func();
|
||||
pure virtual function void assert_func();
|
||||
endclass
|
||||
|
||||
class IfaceClassImpl implements IfaceClass;
|
||||
virtual function void assertoff_func();
|
||||
$assertoff;
|
||||
endfunction
|
||||
virtual function void assert_func();
|
||||
assert(0);
|
||||
endfunction
|
||||
endclass
|
||||
|
||||
module assert_iface_class;
|
||||
IfaceClassImpl ifaceClassImpl = new;
|
||||
initial begin
|
||||
ifaceClassImpl.assertoff_func();
|
||||
ifaceClassImpl.assert_func();
|
||||
end
|
||||
endmodule
|
||||
@ -81,5 +81,11 @@ module Test(/*AUTOARG*/
|
||||
|
||||
always @(posedge clk) begin
|
||||
out <= in;
|
||||
|
||||
// Assert control dump test.
|
||||
$assertoff;
|
||||
$assertkill;
|
||||
assert(0);
|
||||
$asserton;
|
||||
end
|
||||
endmodule
|
||||
|
||||
@ -487,22 +487,47 @@
|
||||
],
|
||||
"lhsp": [
|
||||
{"type":"PARSEREF","name":"out","addr":"(VH)","loc":"d,83:7,83:10","dtypep":"UNLINKED","expect":"TEXT","lhsp": [],"ftaskrefp": []}
|
||||
],"timingControlp": []}
|
||||
],"timingControlp": []},
|
||||
{"type":"ASSERTCTL","name":"","addr":"(WH)","loc":"d,86:7,86:17","ctlType":"$assertoff",
|
||||
"controlTypep": [
|
||||
{"type":"CONST","name":"32'h4","addr":"(XH)","loc":"d,86:7,86:17","dtypep":"(MC)"}
|
||||
],
|
||||
"levelp": [
|
||||
{"type":"CONST","name":"32'h0","addr":"(YH)","loc":"d,86:7,86:17","dtypep":"(MC)"}
|
||||
],"itemsp": []},
|
||||
{"type":"ASSERTCTL","name":"","addr":"(ZH)","loc":"d,87:7,87:18","ctlType":"$assertkill",
|
||||
"controlTypep": [
|
||||
{"type":"CONST","name":"32'h5","addr":"(AI)","loc":"d,87:7,87:18","dtypep":"(MC)"}
|
||||
],
|
||||
"levelp": [
|
||||
{"type":"CONST","name":"32'h0","addr":"(BI)","loc":"d,87:7,87:18","dtypep":"(MC)"}
|
||||
],"itemsp": []},
|
||||
{"type":"ASSERT","name":"","addr":"(CI)","loc":"d,88:7,88:13","immediate":true,
|
||||
"propp": [
|
||||
{"type":"CONST","name":"?32?sh0","addr":"(DI)","loc":"d,88:14,88:15","dtypep":"(L)"}
|
||||
],"sentreep": [],"failsp": [],"passsp": []},
|
||||
{"type":"ASSERTCTL","name":"","addr":"(EI)","loc":"d,89:7,89:16","ctlType":"$asserton",
|
||||
"controlTypep": [
|
||||
{"type":"CONST","name":"32'h3","addr":"(FI)","loc":"d,89:7,89:16","dtypep":"(MC)"}
|
||||
],
|
||||
"levelp": [
|
||||
{"type":"CONST","name":"32'h0","addr":"(GI)","loc":"d,89:7,89:16","dtypep":"(MC)"}
|
||||
],"itemsp": []}
|
||||
]}
|
||||
]}
|
||||
]}
|
||||
],"activesp": []}
|
||||
],"filesp": [],
|
||||
"miscsp": [
|
||||
{"type":"TYPETABLE","name":"","addr":"(C)","loc":"a,0:0,0:0","constraintRefp":"UNLINKED","emptyQueuep":"UNLINKED","queueIndexp":"UNLINKED","streamp":"UNLINKED","voidp":"(WH)",
|
||||
{"type":"TYPETABLE","name":"","addr":"(C)","loc":"a,0:0,0:0","constraintRefp":"UNLINKED","emptyQueuep":"UNLINKED","queueIndexp":"UNLINKED","streamp":"UNLINKED","voidp":"(HI)",
|
||||
"typesp": [
|
||||
{"type":"BASICDTYPE","name":"integer","addr":"(XH)","loc":"c,31:27,31:28","dtypep":"(XH)","keyword":"integer","range":"31:0","generic":true,"rangep": []},
|
||||
{"type":"BASICDTYPE","name":"integer","addr":"(II)","loc":"c,31:27,31:28","dtypep":"(II)","keyword":"integer","range":"31:0","generic":true,"rangep": []},
|
||||
{"type":"BASICDTYPE","name":"logic","addr":"(L)","loc":"c,33:32,33:33","dtypep":"(L)","keyword":"logic","range":"31:0","generic":true,"rangep": []},
|
||||
{"type":"BASICDTYPE","name":"logic","addr":"(UE)","loc":"c,50:22,50:24","dtypep":"(UE)","keyword":"logic","generic":true,"rangep": []},
|
||||
{"type":"VOIDDTYPE","name":"","addr":"(WH)","loc":"c,51:21,51:30","dtypep":"(WH)","generic":false},
|
||||
{"type":"VOIDDTYPE","name":"","addr":"(HI)","loc":"c,51:21,51:30","dtypep":"(HI)","generic":false},
|
||||
{"type":"BASICDTYPE","name":"logic","addr":"(QD)","loc":"c,119:22,119:23","dtypep":"(QD)","keyword":"logic","range":"31:0","generic":true,"rangep": []},
|
||||
{"type":"BASICDTYPE","name":"logic","addr":"(YH)","loc":"c,121:22,121:23","dtypep":"(YH)","keyword":"logic","range":"31:0","generic":true,"rangep": []},
|
||||
{"type":"BASICDTYPE","name":"logic","addr":"(ZH)","loc":"c,156:17,156:56","dtypep":"(ZH)","keyword":"logic","range":"295:0","generic":true,"rangep": []},
|
||||
{"type":"BASICDTYPE","name":"logic","addr":"(JI)","loc":"c,121:22,121:23","dtypep":"(JI)","keyword":"logic","range":"31:0","generic":true,"rangep": []},
|
||||
{"type":"BASICDTYPE","name":"logic","addr":"(KI)","loc":"c,156:17,156:56","dtypep":"(KI)","keyword":"logic","range":"295:0","generic":true,"rangep": []},
|
||||
{"type":"BASICDTYPE","name":"string","addr":"(BG)","loc":"c,156:10,156:16","dtypep":"(BG)","keyword":"string","generic":true,"rangep": []},
|
||||
{"type":"BASICDTYPE","name":"logic","addr":"(Q)","loc":"d,14:9,14:11","dtypep":"(Q)","keyword":"logic","range":"31:0","generic":true,"rangep": []},
|
||||
{"type":"BASICDTYPE","name":"logic","addr":"(BB)","loc":"d,18:10,18:12","dtypep":"(BB)","keyword":"logic","range":"31:0","generic":true,"rangep": []},
|
||||
@ -517,9 +542,9 @@
|
||||
]},
|
||||
{"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0",
|
||||
"modulep": [
|
||||
{"type":"MODULE","name":"@CONST-POOL@","addr":"(AI)","loc":"a,0:0,0:0","origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [],
|
||||
{"type":"MODULE","name":"@CONST-POOL@","addr":"(LI)","loc":"a,0:0,0:0","origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [],
|
||||
"stmtsp": [
|
||||
{"type":"SCOPE","name":"@CONST-POOL@","addr":"(BI)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(AI)","varsp": [],"blocksp": [],"inlinesp": []}
|
||||
{"type":"SCOPE","name":"@CONST-POOL@","addr":"(MI)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(LI)","varsp": [],"blocksp": [],"inlinesp": []}
|
||||
],"activesp": []}
|
||||
]}
|
||||
]}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user