verilator/test_regress/t/t_assert_ctl_immediate_bad.out
Bartłomiej Chmiel 2a9f29912c
Add parameterless assert control system tasks (#5010)
Signed-off-by: Bartłomiej Chmiel <bchmiel@antmicro.com>
Co-authored-by: Ryszard Rozak <rrozak@antmicro.com>
Co-authored-by: Wilson Snyder <wsnyder@wsnyder.org>
Co-authored-by: Arkadiusz Kozdra <akozdra@antmicro.com>
2024-05-08 08:31:34 -04:00

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[0] %Error: t_assert_ctl_immediate_bad.v:50: Assertion failed in top.t.module_with_assertctl: 'assert' failed.
-Info: t/t_assert_ctl_immediate_bad.v:50: Verilog $stop, ignored due to +verilator+error+limit
[0] %Error: t_assert_ctl_immediate_bad.v:54: Assertion failed in top.t.module_with_assertctl: 'assert' failed.
[0] %Error: t_assert_ctl_immediate_bad.v:59: Assertion failed in top.t.module_with_assertctl: 'assert' failed.
[0] %Error: t_assert_ctl_immediate_bad.v:63: Assertion failed in top.t.module_with_assertctl: 'assert' failed.
[0] %Error: t_assert_ctl_immediate_bad.v:68: Assertion failed in top.t.module_with_assertctl: 'assert' failed.
[0] %Error: t_assert_ctl_immediate_bad.v:74: Assertion failed in top.t.module_with_assertctl: 'assert' failed.
[0] %Error: t_assert_ctl_immediate_bad.v:45: Assertion failed in top.t.module_with_assertctl.f_assert: 'assert' failed.
[0] %Error: t_assert_ctl_immediate_bad.v:45: Assertion failed in top.t.module_with_assertctl.f_assert: 'assert' failed.
*-* All Finished *-*