mirror of
https://github.com/verilator/verilator.git
synced 2025-01-05 22:27:35 +00:00
2a9f29912c
Signed-off-by: Bartłomiej Chmiel <bchmiel@antmicro.com> Co-authored-by: Ryszard Rozak <rrozak@antmicro.com> Co-authored-by: Wilson Snyder <wsnyder@wsnyder.org> Co-authored-by: Arkadiusz Kozdra <akozdra@antmicro.com>
23 lines
609 B
Perl
Executable File
23 lines
609 B
Perl
Executable File
#!/usr/bin/env perl
|
|
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
|
|
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
|
#
|
|
# Copyright 2024 by Wilson Snyder. This program is free software; you
|
|
# can redistribute it and/or modify it under the terms of either the GNU
|
|
# Lesser General Public License Version 3 or the Perl Artistic License
|
|
# Version 2.0.
|
|
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
|
|
|
|
scenarios(vlt => 1);
|
|
|
|
compile(
|
|
verilator_flags2 => ["--exe --main --timing --assert"],
|
|
);
|
|
|
|
execute(
|
|
check_finished => 1,
|
|
);
|
|
|
|
ok(1);
|
|
1;
|