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42 lines
529 B
Verilog
42 lines
529 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2007 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Outputs
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ok, o, og, org,
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// Inputs
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i
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);
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reg a;
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reg a;
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integer l;
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integer l;
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bit b;
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bit b;
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output ok;
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reg ok;
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output o;
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output o;
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input i;
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input i;
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output oi;
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input oi;
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output og;
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reg og;
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reg og;
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output reg org;
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output reg org;
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endmodule
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