Fix not reporting some duplicate signals, bug1462.

Changes

@@ -32,6 +32,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
 
 ****  Fix build error on MinGW, bug1460. [Richard Myers]
 
+****  Fix not reporting some duplicate signals, bug1462. [Peter Gerst]
+
 
 * Verilator 4.014 2019-05-08
 

src/V3LinkDot.cpp

@@ -933,10 +933,12 @@ class LinkDotFindVisitor : public AstNVisitor {
                       <<" ;; parent=se"<<cvtToHex(foundp->parentp())<<endl);
                 if (foundp && foundp->parentp() == m_curSymp  // Only when on same level
                     && !foundp->imported()) {  // and not from package
-                    if ((findvarp->isIO() && nodep->isSignal())
-                        || (findvarp->isSignal() && nodep->isIO())) {
+                    if (!(findvarp->isIO() && nodep->isIO())  // e.g. !(output && output)
+                        && ((findvarp->isIO() && nodep->isSignal())  // e.g. output && reg
+                            || (findvarp->isSignal() && nodep->isIO()))  // e.g. reg && output
+                        && !(findvarp->isSignal() && !nodep->isSignal())) {  // e.g. !(reg && reg)
                         findvarp->combineType(nodep);
-                        nodep->fileline()->modifyStateInherit(nodep->fileline());
+                        findvarp->fileline()->modifyStateInherit(nodep->fileline());
                         AstBasicDType* bdtypep = VN_CAST(findvarp->childDTypep(), BasicDType);
                         if (bdtypep && bdtypep->implicit()) {
                             // Then have "input foo" and "real foo" so the
@@ -947,12 +949,15 @@ class LinkDotFindVisitor : public AstNVisitor {
                             newdtypep->unlinkFrBack();
                             findvarp->childDTypep(newdtypep);
                         }
-                        nodep->unlinkFrBack()->deleteTree(); VL_DANGLING(nodep);
                     } else {
                         nodep->v3error("Duplicate declaration of signal: "
                                        <<nodep->prettyName()<<endl
                                        <<findvarp->warnMore()<<"... Location of original declaration");
+                        // Combining most likely reduce other errors
+                        findvarp->combineType(nodep);
+                        findvarp->fileline()->modifyStateInherit(nodep->fileline());
                     }
+                    nodep->unlinkFrBack()->deleteTree(); VL_DANGLING(nodep);
                 } else {
                     // User can disable the message at either point
                     if (!(m_ftaskp && m_ftaskp->dpiImport())

test_regress/t/t_var_dup_bad.out

@@ -0,0 +1,16 @@
+%Error: t/t_var_dup_bad.v:14: Duplicate declaration of signal: a
+        t/t_var_dup_bad.v:13: ... Location of original declaration
+%Error: t/t_var_dup_bad.v:17: Duplicate declaration of signal: l
+        t/t_var_dup_bad.v:16: ... Location of original declaration
+%Error: t/t_var_dup_bad.v:20: Duplicate declaration of signal: b
+        t/t_var_dup_bad.v:19: ... Location of original declaration
+%Error: t/t_var_dup_bad.v:26: Duplicate declaration of signal: o
+        t/t_var_dup_bad.v:25: ... Location of original declaration
+%Error: t/t_var_dup_bad.v:29: Duplicate declaration of signal: i
+        t/t_var_dup_bad.v:28: ... Location of original declaration
+%Error: t/t_var_dup_bad.v:32: Duplicate declaration of signal: oi
+        t/t_var_dup_bad.v:31: ... Location of original declaration
+%Error: t/t_var_dup_bad.v:39: Duplicate declaration of signal: org
+        t/t_var_dup_bad.v:38: ... Location of original declaration
+%Error: t/t_var_dup_bad.v:31: Input/output/inout does not appear in port list: oi
+%Error: Exiting due to

test_regress/t/t_var_dup_bad.pl

@@ -0,0 +1,19 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+scenarios(vlt => 1);
+
+compile(
+    verilator_flags2 => ["--lint-only"],
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;

test_regress/t/t_var_dup_bad.v

@@ -0,0 +1,41 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2007 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Outputs
+   ok, o, og, org,
+   // Inputs
+   i
+   );
+
+   reg    a;
+   reg    a;
+
+   integer l;
+   integer l;
+
+   bit     b;
+   bit     b;
+
+   output ok;
+   reg    ok;
+
+   output o;
+   output o;
+
+   input  i;
+   input  i;
+
+   output oi;
+   input  oi;
+
+   output og;
+   reg    og;
+   reg    og;
+
+   output reg org;
+   output reg org;
+
+endmodule