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73 lines
2.0 KiB
Verilog
73 lines
2.0 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2008 by Wilson Snyder.
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`include "verilated.v"
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module t;
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// Note $sscanf already tested elsewhere
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reg [3:0] n;
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reg [63:0] q;
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reg [16*8:1] wide;
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reg [8:1] ochar;
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reg [48*8:1] str;
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reg [48*8:1] str2;
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string str3;
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real r;
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initial begin
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n = 4'b1100;
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q = 64'h1234_5678_abcd_0123;
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wide = "hello-there12345";
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$sformat(str, "n=%b q=%d w=%s", n, q, wide);
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`ifdef TEST_VERBOSE $display("str=%0s",str); `endif
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if (str !== "n=1100 q= 1311768467750060323 w=hello-there12345") $stop;
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q = {q[62:0],1'b1};
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$swrite(str2, "n=%b q=%d w=%s", n, q, wide);
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`ifdef TEST_VERBOSE $display("str2=%0s",str2); `endif
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if (str2 !== "n=1100 q= 2623536935500120647 w=hello-there12345") $stop;
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str3 = $sformatf("n=%b q=%d w=%s", n, q, wide);
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`ifdef TEST_VERBOSE $display("str3=%0s",str3); `endif
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if (str3 !== "n=1100 q= 2623536935500120647 w=hello-there12345") $stop;
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$swrite(str2, "e=%e", r);
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$swrite(str2, "e=%f", r);
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$swrite(str2, "e=%g", r);
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r = 0.01;
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$swrite(str2, "e=%e f=%f g=%g", r, r, r);
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`ifdef TEST_VERBOSE $display("str2=%0s",str2); `endif
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if (str2 !== "e=1.000000e-02 f=0.010000 g=0.01") $stop;
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$swrite(str2, "mod=%m");
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`ifdef TEST_VERBOSE $display("str2=%0s",str2); `endif
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if (str2 !== "mod=top.t") $stop;
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$swrite(str2, "lib=%l");
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`ifdef TEST_VERBOSE $display("chkl %0s",str2); `endif
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if (str2 !== "lib=t") $stop;
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str3 = $sformatf("u=%u", {"a","b","c","d"}); // Value selected so is printable
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`ifdef TEST_VERBOSE $display("chku %s %s",str3,str3); `endif
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if (str3 !== "u=dcba") $stop;
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str3 = $sformatf("v=%v", {"a","b","c","d"}); // Value selected so is printable
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`ifdef TEST_VERBOSE $display("chkv %s %s",str3,str3); `endif
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$sformat(ochar,"%s","c");
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if (ochar != "c") $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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