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Tests: Remove tabs from golden-output tests. No functional change.

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This commit is contained in:
Wilson Snyder 2019-06-12 22:41:51 -04:00
parent b3e2d26e35
commit e4a3f9b38c
12 changed files with 87 additions and 87 deletions
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2
test_regress/t/.gitattributes vendored
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@ -1 +1 @@
t_dos*.pl -crlf
t_dos*.pl -crlf

42
test_regress/t/t_EXAMPLE.v
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@ -2,8 +2,8 @@
//
// Use this file as a template for submitting bugs, etc.
// This module takes a single clock input, and should either
// $write("*-* All Finished *-*\n");
// $finish;
// $write("*-* All Finished *-*\n");
// $finish;
// on success, or $stop.
//
// The code as shown applies a random vector to the Test
@ -21,24 +21,24 @@ module t (/*AUTOARG*/
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] out; // From test of Test.v
wire [31:0] out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[31:0]),
// Inputs
.clk (clk),
.in (in[31:0]));
// Outputs
.out (out[31:0]),
// Inputs
.clk (clk),
.in (in[31:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {32'h0, out};
@ -52,23 +52,23 @@ module t (/*AUTOARG*/
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= '0;
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= '0;
end
else if (cyc<10) begin
sum <= '0;
sum <= '0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h4afe43fb79d7b71e
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end

4
test_regress/t/t_bitsel_enum.v
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@ -12,8 +12,8 @@ module t_bitsel_enum
localparam [6:0] CNST_VAL = 7'h22;
enum logic [6:0] {
ENUM_VAL = 7'h33
} MyEnum;
ENUM_VAL = 7'h33
} MyEnum;
assign out0 = CNST_VAL[0];
// Not supported by NC-verilog nor VCS, but other simulators do

2
test_regress/t/t_dist_manifest.pl
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@ -43,7 +43,7 @@ if (! -d $git_dir) {
my $git_exclude = `cd $root && git ls-files --others --ignored --exclude-from $git_dir/info/exclude`;
foreach my $exclude (split /\s+/, $git_exclude) {
if (exists $files{$exclude}) {
$files{$exclude} |= 8;
$files{$exclude} |= 8;
}
}

34
test_regress/t/t_dpi_accessors_inc.vh
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@ -11,26 +11,26 @@
// Use the macros to provide the desire access to our data. First simple
// access to the registers, array elements and wires. For consistency with
// simulators, we do not attempt to write wires.
`RW_ACCESS ([0:0], a, {t.i_test_sub.a});
`RW_ACCESS ([7:0], b, {t.i_test_sub.b});
`RW_ACCESS ([7:0], mem32, {t.i_test_sub.mem[32]});
`R_ACCESS ([0:0], c, {t.i_test_sub.c});
`R_ACCESS ([7:0], d, {t.i_test_sub.d});
`RW_ACCESS ([7:0], e, {t.i_test_sub.e});
`RW_ACCESS ([7:0], f, {t.i_test_sub.f});
`RW_ACCESS([0:0], a, {t.i_test_sub.a});
`RW_ACCESS([7:0], b, {t.i_test_sub.b});
`RW_ACCESS([7:0], mem32, {t.i_test_sub.mem[32]});
`R_ACCESS ([0:0], c, {t.i_test_sub.c});
`R_ACCESS ([7:0], d, {t.i_test_sub.d});
`RW_ACCESS([7:0], e, {t.i_test_sub.e});
`RW_ACCESS([7:0], f, {t.i_test_sub.f});
// Slices of vectors and array elements. For consistency with simulators,
// we do not attempt to write wire slices.
`RW_ACCESS ([3:0], b_slice, {t.i_test_sub.b[3:0]});
`RW_ACCESS ([4:0], mem32_slice,
{t.i_test_sub.mem[32][7:6],t.i_test_sub.mem[32][2:0]});
`R_ACCESS ([5:0], d_slice, {t.i_test_sub.d[6:1]});
`RW_ACCESS([3:0], b_slice, {t.i_test_sub.b[3:0]});
`RW_ACCESS([4:0], mem32_slice,
{t.i_test_sub.mem[32][7:6], t.i_test_sub.mem[32][2:0]});
`R_ACCESS([5:0], d_slice, {t.i_test_sub.d[6:1]});
// Complex registers, one with distinct read and write. We avoid use of
// wires for consistency with simulators.
`RW_ACCESS ([14:0], l1, {t.i_test_sub.b[3:0],
t.i_test_sub.mem[32][7:6],
t.i_test_sub.e[6:1],
t.i_test_sub.mem[32][2:0]});
`R_ACCESS ([7:0], l2, {t.i_test_sub.e[7:4], t.i_test_sub.f[3:0]});
`W_ACCESS ([7:0], l2, {t.i_test_sub.e[5:2], t.i_test_sub.f[5:2]});
`RW_ACCESS([14:0], l1, {t.i_test_sub.b[3:0],
t.i_test_sub.mem[32][7:6],
t.i_test_sub.e[6:1],
t.i_test_sub.mem[32][2:0]});
`R_ACCESS([7:0], l2, {t.i_test_sub.e[7:4], t.i_test_sub.f[3:0]});
`W_ACCESS([7:0], l2, {t.i_test_sub.e[5:2], t.i_test_sub.f[5:2]});

4
test_regress/t/t_interface_mp_func.v
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@ -5,8 +5,8 @@
interface pads_if();
modport mp_dig(
import fIn,
import fOut );
import fIn,
import fOut );
integer exists[8];
function automatic integer fIn (integer i);

42
test_regress/t/t_lint_syncasyncnet_bad.v
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@ -9,25 +9,25 @@ module t (/*AUTOARG*/
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input clk; // To sub1 of sub1.v, ...
input d; // To sub1 of sub1.v, ...
input rst_async_l; // To sub2 of sub2.v
input rst_both_l; // To sub1 of sub1.v, ...
input rst_sync_l; // To sub1 of sub1.v
input clk; // To sub1 of sub1.v, ...
input d; // To sub1 of sub1.v, ...
input rst_async_l; // To sub2 of sub2.v
input rst_both_l; // To sub1 of sub1.v, ...
input rst_sync_l; // To sub1 of sub1.v
// End of automatics
sub1 sub1 (/*AUTOINST*/
// Inputs
.clk (clk),
.rst_both_l (rst_both_l),
.rst_sync_l (rst_sync_l),
.d (d));
// Inputs
.clk (clk),
.rst_both_l (rst_both_l),
.rst_sync_l (rst_sync_l),
.d (d));
sub2 sub2 (/*AUTOINST*/
// Inputs
.clk (clk),
.rst_both_l (rst_both_l),
.rst_async_l (rst_async_l),
.d (d));
// Inputs
.clk (clk),
.rst_both_l (rst_both_l),
.rst_async_l (rst_async_l),
.d (d));
endmodule
module sub1 (/*AUTOARG*/
@ -46,9 +46,9 @@ module sub1 (/*AUTOARG*/
always @(posedge clk) begin
if (~rst_sync_l) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
q1 <= 1'h0;
// End of automatics
// Beginning of autoreset for uninitialized flops
q1 <= 1'h0;
// End of automatics
end else begin
q1 <= d;
end
@ -78,9 +78,9 @@ module sub2 (/*AUTOARG*/
always @(posedge clk or negedge rst_async_l) begin
if (~rst_async_l) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
q1 <= 1'h0;
// End of automatics
// Beginning of autoreset for uninitialized flops
q1 <= 1'h0;
// End of automatics
end else begin
q1 <= d;
end

4
test_regress/t/t_mem_packed_assign.v
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@ -28,8 +28,8 @@ module t (/*AUTOARG*/
$write("cyc%0d c:%0x a0:%0x a1:%0x a2:%0x a3:%0x\n", cyc, arr_c, arr[0], arr[1], arr[2], arr[3]);
`endif
if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
$write("*-* All Finished *-*\n");
$finish;
end
end

14
test_regress/t/t_select_bad_range2.v
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@ -13,16 +13,16 @@ module t (/*AUTOARG*/
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [1:0] out10; // From test of Test.v
wire [1:0] out32; // From test of Test.v
wire [1:0] out10; // From test of Test.v
wire [1:0] out32; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out32 (out32[1:0]),
.out10 (out10[1:0]),
// Inputs
.in (in[1:0]));
// Outputs
.out32 (out32[1:0]),
.out10 (out10[1:0]),
// Inputs
.in (in[1:0]));
// Test loop
always @ (posedge clk) begin

4
test_regress/t/t_sys_sformat.v
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@ -13,13 +13,13 @@ module t;
reg [63:0] q;
reg [16*8:1] wide;
reg [8:1] ochar;
reg [8:1] ochar;
reg [48*8:1] str;
reg [48*8:1] str2;
string str3;
real r;
real r;
initial begin
n = 4'b1100;

4
test_regress/t/t_tri_ifbegin.v
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@ -6,8 +6,8 @@ module t (/*AUTOARG*/
);
input clk;
tri pad_io_h;
tri pad_io_l;
tri pad_io_h;
tri pad_io_l;
sub sub (.*);

18
test_regress/t/t_unopt_combo.v
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@ -19,18 +19,18 @@ module t (/*AUTOARG*/
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] b; // From file of file.v
wire [31:0] c; // From file of file.v
wire [31:0] d; // From file of file.v
wire [31:0] b; // From file of file.v
wire [31:0] c; // From file of file.v
wire [31:0] d; // From file of file.v
// End of automatics
file file (/*AUTOINST*/
// Outputs
.b (b[31:0]),
.c (c[31:0]),
.d (d[31:0]),
// Inputs
.crc (crc[31:0]));
// Outputs
.b (b[31:0]),
.c (c[31:0]),
.d (d[31:0]),
// Inputs
.crc (crc[31:0]));
always @ (posedge clk) begin
`ifdef TEST_VERBOSE