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- Change .cvsignore to .gitignore - Remove Id metacomments - Cleanup whitespace at end of lines
73 lines
1.8 KiB
Verilog
73 lines
1.8 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2005 by Wilson Snyder.
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// verilator metacomment preserved
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/**/
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/*verilator metacomment also_preserved*/
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Hello in t_preproc_psl.v
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// Psl capitalized not relevant
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// Double commented ignored // psl not ok
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// You can't have multiple statements on one // psl line.
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// Inline /*cmt*/ comments not allowed inside psl comments
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// psl default clock = (posedge clk);
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// psl fails1: cover {cyc==10};
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// psl assert always cyc!=10;
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// psl assert always cyc==3 -> mask==8'h2;
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// psl failsx: cover {cyc==3 && mask==8'h1};
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/* psl fails2:
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cover {
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cyc==3 && mask==8'h9};
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// Ignore this comment-in-between-statements (however not legal inside a statement)
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fails3: always assert {
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cyc==3 && mask==8'h10 };
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*/
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`__LINE__
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// Note the PSL statement can be on a unique line
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// There can also be multiple "psl" keywords per line.
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/*
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psl
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fails_ml:
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assert always
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cyc==3 -> mask==8'h21;
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psl
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fails_mlalso: assert always cyc==3 -> mask==8'h21;
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*/
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`__LINE__
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// psl assert never (cyc==1 && reset_l);
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// psl fails3: assert always
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// cyc==3 -> mask==8'h21;
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// syntax_error, not_part_of_above_stmt;
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// We need to count { and ( when looking for ; that terminate a PSL expression
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// psl assert always
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// {[*]; cyc==3;
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// cyc==4; cyc==6};
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// syntax_error, not_part_of_above_stmt;
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// However /**/ pairs can't be split as above.
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`ifdef NEVER
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// psl ifdefs have precedence;
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`endif
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// Macros are expanded...
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`define define_sig cyc
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// psl assert always `define_sig!=10;
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`ifdef verilator
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`psl
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psl assert always sig!=90;
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`verilog
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`endif
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// Did we end up right?
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`__LINE__
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