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- Change .cvsignore to .gitignore - Remove Id metacomments - Cleanup whitespace at end of lines
44 lines
812 B
Verilog
44 lines
812 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2007 by Wilson Snyder.
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module t (/*AUTOARG*/);
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integer num;
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initial begin
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num = 0;
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`define EMPTY_TRUE
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`ifndef EMPTY_TRUE
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`error "Empty is still true"
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`endif
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`define A
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`ifdef A $display("1A"); num = num + 1;
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`ifdef C $stop;
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`elsif A $display("2A"); num = num + 1;
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`ifdef C $stop;
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`elsif B $stop;
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`else $display("3A"); num = num + 1;
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`endif
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`else $stop;
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`endif
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`elsif B $stop;
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`ifdef A $stop;
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`elsif A $stop;
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`else
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`endif
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`elsif C $stop;
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`else $stop;
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`endif
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if (num == 3) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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else begin
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$write("%%Error: Bad count: %d\n", num);
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$stop;
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end
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end
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endmodule
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