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56 lines
1.0 KiB
Verilog
56 lines
1.0 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2005 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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parameter PAR = 3;
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input clk;
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m3 m3_inst (.clk(clk));
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defparam m3_inst.FROMDEFP = 19;
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defparam m3_inst.P2 = 2;
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//defparam m3_inst.P3 = PAR;
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defparam m3_inst.P3 = 3;
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integer cyc=1;
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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if (cyc==1) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module m3
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(/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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localparam LOC = 13;
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parameter UNCH = 99;
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parameter P1 = 10;
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parameter P2 = 20;
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parameter P3 = 30;
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parameter FROMDEFP = 11;
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initial begin
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$display("%x %x %x",P1,P2,P3);
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end
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always @ (posedge clk) begin
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if (UNCH !== 99) $stop;
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if (P1 !== 10) $stop;
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if (P2 !== 2) $stop;
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if (P3 !== 3) $stop;
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if (FROMDEFP !== 19) $stop;
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end
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endmodule
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