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- Change .cvsignore to .gitignore - Remove Id metacomments - Cleanup whitespace at end of lines
13 lines
265 B
Verilog
13 lines
265 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2003-2007 by Wilson Snyder.
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module t;
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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