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65 lines
2.0 KiB
Systemverilog
65 lines
2.0 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2020 by Yutetsu TAKATSUKASA
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// SPDX-License-Identifier: Unlicense
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module t (
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clk
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);
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input clk;
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int c = 0;
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t2 #(0) i_0(.*);
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t2 #(-1) i_1(.*); // lo is -1, hi is 5
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t2 #(-4) i_2(.*); // lo is -4, hi is 1
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t2 #(-10) i_3(.*); // lo is -10, hi is -4
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t2 #(+1) i_4(.*); // lo is 1, hi is 7
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t2 #(+4) i_5(.*); // lo is 4, hi is 10
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t2 #(+10) i_6(.*); // lo is 10, hi is 16
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always @(posedge clk) begin
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c <= c + 1;
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if (c == 5) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module t2 #(parameter ORIGIN = 0) (input wire clk, input int c);
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localparam WIDTH = 7;
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localparam OFFSET = 3;
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localparam FULL_LO = ORIGIN;
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localparam FULL_HI = ORIGIN + WIDTH - 1;
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localparam PART_LO = FULL_LO + OFFSET;
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localparam PART_HI = FULL_HI;
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logic unpack_sig0 [FULL_LO:FULL_HI];
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logic unpack_sig1 [PART_LO:PART_HI];
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logic unpack_sig2 [FULL_HI:FULL_LO];
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logic unpack_sig3 [PART_HI:PART_LO];
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initial $display("%m ORIGIN:%d [%d:%d] [%d:%d]", ORIGIN, FULL_LO, FULL_HI, PART_LO, PART_HI);
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always @(posedge clk) begin
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unpack_sig0[PART_LO] <= 1'b1;
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unpack_sig1[PART_LO] <= 1'b1;
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unpack_sig0 [PART_LO+1:FULL_HI] <= unpack_sig0[PART_LO:FULL_HI-1];
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unpack_sig1 [PART_LO+1:PART_HI] <= unpack_sig1[PART_LO:PART_HI-1];
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unpack_sig2[PART_LO] <= 1'b1;
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unpack_sig3[PART_LO] <= 1'b1;
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unpack_sig2 [FULL_HI:PART_LO+1] <= unpack_sig2[FULL_HI-1:PART_LO];
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unpack_sig3 [PART_HI:PART_LO+1] <= unpack_sig3[PART_HI-1:PART_LO];
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end
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always @(posedge clk) begin
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if (c >= 4) begin
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if (!unpack_sig0[FULL_HI] || !unpack_sig1[PART_HI]) $stop;
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if (!unpack_sig2[FULL_HI] || !unpack_sig3[PART_HI]) $stop;
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end else begin
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if (unpack_sig0[FULL_HI] || unpack_sig1[PART_HI]) $stop;
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if (unpack_sig2[FULL_HI] || unpack_sig3[PART_HI]) $stop;
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end
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end
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endmodule
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