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3f89bdcfac
No functional change. Postpone the conversion of all AstAssignDlys that use the 'VdlySet' scheme for array LHSs until after the complete traversal of the netlist. The next patch takes advantage of this by using some extra information also gathered through the traversal to change the conversion. AstAssignDlys inside suspendable or fork are not deferred and are processed identical to the previous version. There are some TODOs in this patch that are fixed in the next patch. Output code perturbed due to variable ordering. MULTIDRIVEN message ordering perturbed due to processing order change. |
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| _static | ||
| bin | ||
| gen | ||
| guide | ||
| .gitignore | ||
| CONTRIBUTING.rst | ||
| CONTRIBUTORS | ||
| internals.rst | ||
| Makefile | ||
| README.rst | ||
| spelling.txt | ||
| verilated.dox | ||
| xml.rst | ||
Verilator Documentation ======================= This folder contains sources for Verilator documentation. For formatted documentation see: - `Verilator README <https://github.com/verilator/verilator>`_ - `Verilator installation and package directory structure <https://verilator.org/install>`_ - `Verilator manual (HTML) <https://verilator.org/verilator_doc.html>`_, or `Verilator manual (PDF) <https://verilator.org/verilator_doc.pdf>`_ - `Subscribe to Verilator announcements <https://github.com/verilator/verilator-announce>`_ - `Verilator forum <https://verilator.org/forum>`_ - `Verilator issues <https://verilator.org/issues>`_