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28 lines
830 B
Systemverilog
28 lines
830 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define PREFIX_ my_prefix_
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`define SUFFIX my_suffix
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`define PREFIX_SUFFIX my_prefix_suffix
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`define name1 `PREFIX``_```SUFFIX
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`define name2(p,s) p``_``s
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`define name3(p) ```p``_SUFFIX
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`define stringify(text) `"text`"
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module t();
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initial begin
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// Another simulator gives:
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// `PREFIX_my_suffix
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// `name2(`PREFIX, my_suffix)
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// `name3(PREFIX)
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$display(`stringify(`name1));
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$display(`stringify(`name2(`PREFIX, `SUFFIX)));
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$display(`stringify(`name3(PREFIX)));
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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