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36 lines
733 B
Systemverilog
36 lines
733 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (clk);
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input clk;
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integer cyc = 0;
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 5) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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mid mid_a(clk);
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mid mid_b(clk);
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mid mid_c(clk);
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endmodule
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module mid(input wire clk);
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int cnt = 0;
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always @(posedge clk) cnt += 1;
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sub sub_a(clk);
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sub sub_b(clk);
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sub sub_c(clk);
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endmodule
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module sub(input wire clk);
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int cnt = 0;
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always @(posedge clk) cnt += 2;
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endmodule
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