Fix tracing_{on,off} in the presence of non-inlined modules (#5346)

Previously "*.foo.*" failed to match non-inlined instances called 'foo'.

src/V3TraceDecl.cpp

@@ -173,7 +173,7 @@ class TraceDeclVisitor final : public VNVisitor {
         } else if (!nodep->isTrace()) {
             return "Verilator instance trace_off";
         } else {
-            const string prettyName = varp->prettyName();
+            const string prettyName = nodep->prettyName();
             if (!v3Global.opt.traceUnderscore()) {
                 if (!prettyName.empty() && prettyName[0] == '_') return "Leading underscore";
                 if (prettyName.find("._") != string::npos) return "Inlined leading underscore";

test_regress/t/t_trace_scope_no_inline.out

@@ -0,0 +1,81 @@
+$version Generated by VerilatedVcd $end
+$timescale 1ps $end
+ $scope module top $end
+  $scope module t $end
+   $scope module mid_a $end
+   $upscope $end
+   $scope module mid_b $end
+    $var wire 1 ' clk $end
+    $var wire 32 # cnt [31:0] $end
+    $scope module sub_a $end
+     $var wire 1 ' clk $end
+     $var wire 32 $ cnt [31:0] $end
+    $upscope $end
+    $scope module sub_b $end
+     $var wire 1 ' clk $end
+     $var wire 32 % cnt [31:0] $end
+    $upscope $end
+    $scope module sub_c $end
+     $var wire 1 ' clk $end
+     $var wire 32 & cnt [31:0] $end
+    $upscope $end
+   $upscope $end
+   $scope module mid_c $end
+   $upscope $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#0
+b00000000000000000000000000000000 #
+b00000000000000000000000000000000 $
+b00000000000000000000000000000000 %
+b00000000000000000000000000000000 &
+0'
+#10
+b00000000000000000000000000000001 #
+b00000000000000000000000000000010 $
+b00000000000000000000000000000010 %
+b00000000000000000000000000000010 &
+1'
+#15
+0'
+#20
+b00000000000000000000000000000010 #
+b00000000000000000000000000000100 $
+b00000000000000000000000000000100 %
+b00000000000000000000000000000100 &
+1'
+#25
+0'
+#30
+b00000000000000000000000000000011 #
+b00000000000000000000000000000110 $
+b00000000000000000000000000000110 %
+b00000000000000000000000000000110 &
+1'
+#35
+0'
+#40
+b00000000000000000000000000000100 #
+b00000000000000000000000000001000 $
+b00000000000000000000000000001000 %
+b00000000000000000000000000001000 &
+1'
+#45
+0'
+#50
+b00000000000000000000000000000101 #
+b00000000000000000000000000001010 $
+b00000000000000000000000000001010 %
+b00000000000000000000000000001010 &
+1'
+#55
+0'
+#60
+b00000000000000000000000000000110 #
+b00000000000000000000000000001100 $
+b00000000000000000000000000001100 %
+b00000000000000000000000000001100 &
+1'

test_regress/t/t_trace_scope_no_inline.pl

@@ -0,0 +1,24 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt => 1);
+
+compile(
+    verilator_flags2 => ["--cc --trace -fno-inline t/$Self->{name}.vlt"],
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+vcd_identical($Self->trace_filename, $Self->{golden_filename});
+
+ok(1);
+1;

test_regress/t/t_trace_scope_no_inline.v

@@ -0,0 +1,35 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2024 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (clk);
+   input clk;
+   integer      cyc = 0;
+
+   always @ (posedge clk) begin
+      cyc <= cyc + 1;
+      if (cyc == 5) begin
+         $write("*-* All Finished *-*\n");
+         $finish;
+      end
+   end
+
+   mid mid_a(clk);
+   mid mid_b(clk);
+   mid mid_c(clk);
+endmodule
+
+module mid(input wire clk);
+   int cnt = 0;
+   always @(posedge clk) cnt += 1;
+   sub sub_a(clk);
+   sub sub_b(clk);
+   sub sub_c(clk);
+endmodule
+
+module sub(input wire clk);
+   int cnt = 0;
+   always @(posedge clk) cnt += 2;
+endmodule

test_regress/t/t_trace_scope_no_inline.vlt

@@ -0,0 +1,12 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2024 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+`verilator_config
+
+// Turn tracing off for all scopes by default
+tracing_off -scope "*" -levels 0
+// Turn it back on only for *.mid_b.* and below
+tracing_on -scope "*.mid_b.*" -levels 0