mirror of
https://github.com/verilator/verilator.git
synced 2025-01-09 16:17:36 +00:00
29 lines
501 B
Systemverilog
29 lines
501 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
|
|
//
|
|
// This file ONLY is placed under the Creative Commons Public Domain, for
|
|
// any use, without warranty, 2020 by Wilson Snyder.
|
|
// SPDX-License-Identifier: CC0-1.0
|
|
|
|
class Base;
|
|
endclass
|
|
class C;
|
|
endclass
|
|
|
|
module t (/*AUTOARG*/);
|
|
int i;
|
|
|
|
Base b;
|
|
C c;
|
|
|
|
initial begin
|
|
b = new;
|
|
i = $cast(c, b);
|
|
if (i != 0) $stop;
|
|
|
|
$cast(c, b); // Bad at runtime
|
|
|
|
$write("*-* All Finished *-*\n");
|
|
$finish;
|
|
end
|
|
endmodule
|