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29 lines
501 B
Systemverilog
29 lines
501 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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class Base;
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endclass
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class C;
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endclass
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module t (/*AUTOARG*/);
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int i;
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Base b;
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C c;
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initial begin
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b = new;
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i = $cast(c, b);
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if (i != 0) $stop;
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$cast(c, b); // Bad at runtime
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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