Geza Lore d330100542 Create implicit nets for inputs of gate primitives. ... Prior to this we failed to create implicit nets for inputs of gate primitives, which is required by the standard (IEEE 1800-2017 6.10). Note: outputs were covered due to being modeled as the LHS of assignments, which do create implicit nets.		2023-10-21 22:45:26 +01:00
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_static	Fix Codacy warnings. No functional change.	2021-07-07 19:42:49 -04:00
bin	Internals: Fix some lint-py warnings	2023-10-21 12:48:36 -04:00
gen	Split WIDTH warning into WIDTHEXPAND and WIDTHTRUNC (#3900)	2023-02-02 18:25:25 -05:00
guide	Improve --prof-exec infrastructure and report	2023-10-21 21:09:03 +01:00
.gitignore	Spelling fixes.	2022-05-14 16:12:57 -04:00
CONTRIBUTING.rst	Commentary: Update CONTRIBUTING and internals xrefs (#4043)	2023-03-18 10:23:19 -04:00
CONTRIBUTORS	Create implicit nets for inputs of gate primitives.	2023-10-21 22:45:26 +01:00
internals.rst	Commentary (#4517)	2023-09-23 09:04:35 -04:00
Makefile	Documentation: Drop analytics_id unless VERILATOR_ANALYTICS_ID set (#4333)	2023-07-07 10:44:33 -04:00
spelling.txt	Commentary: Changes update	2023-10-04 20:17:14 -04:00
verilated.dox	Cleanup missing copyrights and those on simply copied files. No functional change.	2023-01-20 20:42:30 -05:00
xml.rst	Cleanup missing copyrights and those on simply copied files. No functional change.	2023-01-20 20:42:30 -05:00