mirror of
https://github.com/verilator/verilator.git
synced 2025-01-09 16:17:36 +00:00
15 lines
343 B
Systemverilog
15 lines
343 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias'
|
|
//
|
|
// Simple bi-directional alias test.
|
|
//
|
|
// This file ONLY is placed under the Creative Commons Public Domain, for
|
|
// any use, without warranty, 2024 by Wilson Snyder.
|
|
// SPDX-License-Identifier: CC0-1.0
|
|
|
|
module t (/*AUTOARG*/);
|
|
|
|
triand ta;
|
|
trior to;
|
|
|
|
endmodule
|