verilator/test_regress/t/t_lib_prot_delay_bad.v
2022-10-22 13:45:48 -04:00

12 lines
270 B
Systemverilog

// DESCRIPTION: Verilator: Verilog Test module
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2019 by Todd Strader.
// SPDX-License-Identifier: CC0-1.0
module secret_impl;
initial begin
#10;
$stop;
end
endmodule