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- Change .cvsignore to .gitignore - Remove Id metacomments - Cleanup whitespace at end of lines
44 lines
1.2 KiB
Verilog
44 lines
1.2 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2003 by Wilson Snyder.
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`include "verilated.v"
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module t;
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`verilator_file_descriptor file;
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initial begin
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// Display formatting
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`ifdef verilator
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if (file != 0) $stop;
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$fwrite(file, "Never printed, file closed\n");
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`endif
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file = $fopen("obj_dir/t_sys_file_test.log","w"); // The "w" is required so we get a FD not a MFD
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$fdisplay(file, "[%0t] hello v=%x", $time, 32'h12345667);
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$fwrite(file, "[%0t] %s\n", $time, "Hello2");
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$fclose(file);
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`ifdef verilator
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if (file != 0) $stop(1); // Also test arguments to stop
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$fwrite(file, "Never printed, file closed\n");
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`endif
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begin
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file = $fopen("obj_dir/DOES_NOT_EXIST","r"); // The "r" is required so we get a FD not a MFD
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if (|file) $stop; // Should not exist, IE must return 0
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end
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begin
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// Check quadword access; a little strange, but it's legal to open "."
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file = $fopen(".","r");
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$fclose(file);
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end
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$write("*-* All Finished *-*\n");
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$finish(0); // Test arguments to finish
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end
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endmodule
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