verilator/test_regress/t/t_sys_readmem_h.mem
Wilson Snyder 52912c6329 Convert repository to git from svn.
- Change .cvsignore to .gitignore
- Remove Id metacomments
- Cleanup whitespace at end of lines
2008-06-09 21:25:10 -04:00

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// DESCRIPTION: Verilator: Verilog Test data file
//
// Copyright 2006 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// General Public License or the Perl Artistic License.
@4
4004_37654321_27654321_17654321_07654321_abcdef10
@a
400a_37654321_27654321_17654321_07654321_abcdef11
400b_37654321_27654321_17654321_07654321_abcdef12
400c_37654321_27654321_17654321_07654321_abcdef13