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88 lines
2.1 KiB
Verilog
88 lines
2.1 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2008 by Wilson Snyder.
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`ifdef verilator
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`define CLOG2 $clog2
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`else
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`define CLOG2 clog2_emulate
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`endif
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc=0;
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reg [63:0] crc;
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reg [63:0] sum;
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wire [31:0] out = `CLOG2(crc[31:0]);
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wire [31:0] out2 = `CLOG2(crc);
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// Aggregate outputs into a single result vector
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wire [63:0] result = {out2, out};
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`define EXPECTED_SUM 64'hc402f59e3d971718
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// Test loop
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always @ (posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
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sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
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if (cyc==0) begin
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crc <= 64'h0;
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if (`CLOG2(32'h0) != 0) $stop;
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if (`CLOG2(32'h1) != 1) $stop;
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if (`CLOG2(32'h7) != 3) $stop;
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if (`CLOG2(32'h8) != 4) $stop;
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if (`CLOG2(32'h9) != 4) $stop;
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if (`CLOG2({32{1'b1}}) != 32) $stop;
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if (`CLOG2({64{1'b1}}) != 64) $stop;
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if (`CLOG2({128{1'b1}}) != 128) $stop;
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end
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else if (cyc==1) begin
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crc <= 64'h1;
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if (result != {32'd0, 32'd0}) $stop;
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end
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else if (cyc==2) begin
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crc <= 64'h3;
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if (result != {32'd1, 32'd1}) $stop;
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end
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else if (cyc==3) begin
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crc <= {64{1'b1}};
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if (result != {32'd2, 32'd2}) $stop;
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end
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else if (cyc==4) begin
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if (result != {32'd64, 32'd32}) $stop;
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end
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else if (cyc==8) begin
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crc <= 64'h5aef0c8d_d70a4497;
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end
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else if (cyc<10) begin
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sum <= 64'h0;
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end
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else if (cyc<90) begin
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end
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else if (cyc==99) begin
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$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
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if (crc !== 64'hcbc77bb9b3784ea0) $stop;
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if (sum !== `EXPECTED_SUM) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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function integer clog2_emulate(input [130:0] arg);
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begin
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for(clog2_emulate=0; arg>0; clog2_emulate=clog2_emulate+1)
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arg = (arg >> 1);
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end
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endfunction
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endmodule
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