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22 lines
431 B
Verilog
22 lines
431 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2005 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Inputs
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value
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);
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input [3:0] value;
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assign value = 4'h0;
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sub sub (.valueSub (value[3:0]));
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endmodule
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module sub (/*AUTOARG*/
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// Inputs
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valueSub
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);
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input [3:0] valueSub;
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assign valueSub = 4'h0;
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endmodule
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