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20 lines
421 B
Systemverilog
20 lines
421 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2009 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/);
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enum bit [1:0] { BADX = 2'b1x } BAD1;
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enum logic [3:0] { e0 = 4'b1xx1,
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e1
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} BAD2;
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initial begin
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$stop;
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end
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endmodule
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