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37 lines
1.7 KiB
Systemverilog
37 lines
1.7 KiB
Systemverilog
// DESCRIPTION: Verilator: Accessor definitions for test of DPI accessors
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2012.
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// Contributed by Jeremy Bennett and Jie Xu
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// See t_dpi_accessors.v for details of the test. This file should be included
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// by the top level module to define all the accessors needed.
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// Use the macros to provide the desire access to our data. First simple
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// access to the registers, array elements and wires. For consistency with
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// simulators, we do not attempt to write wires.
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`RW_ACCESS([0:0], a, {t.i_test_sub.a});
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`RW_ACCESS([7:0], b, {t.i_test_sub.b});
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`RW_ACCESS([7:0], mem32, {t.i_test_sub.mem[32]});
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`R_ACCESS ([0:0], c, {t.i_test_sub.c});
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`R_ACCESS ([7:0], d, {t.i_test_sub.d});
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`RW_ACCESS([7:0], e, {t.i_test_sub.e});
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`RW_ACCESS([7:0], f, {t.i_test_sub.f});
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// Slices of vectors and array elements. For consistency with simulators,
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// we do not attempt to write wire slices.
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`RW_ACCESS([3:0], b_slice, {t.i_test_sub.b[3:0]});
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`RW_ACCESS([4:0], mem32_slice,
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{t.i_test_sub.mem[32][7:6], t.i_test_sub.mem[32][2:0]});
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`R_ACCESS([5:0], d_slice, {t.i_test_sub.d[6:1]});
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// Complex registers, one with distinct read and write. We avoid use of
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// wires for consistency with simulators.
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`RW_ACCESS([14:0], l1, {t.i_test_sub.b[3:0],
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t.i_test_sub.mem[32][7:6],
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t.i_test_sub.e[6:1],
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t.i_test_sub.mem[32][2:0]});
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`R_ACCESS([7:0], l2, {t.i_test_sub.e[7:4], t.i_test_sub.f[3:0]});
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`W_ACCESS([7:0], l2, {t.i_test_sub.e[5:2], t.i_test_sub.f[5:2]});
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