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15 lines
373 B
Systemverilog
15 lines
373 B
Systemverilog
// DESCRIPTION: Verilator: Verilog example module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2017 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// See also https://verilator.org/guide/latest/examples.html"
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module top;
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initial begin
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$display("Hello World!");
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$finish;
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end
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endmodule
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