4 Commits

Author	SHA1	Message	Date
Wilson Snyder	c52ba28dd0	Tests: Fix commentary to unify issue references.	2023-09-15 18:12:11 -04:00
Wilson Snyder	30d6edd2e5	Cleanup missing copyrights and those on simply copied files. No functional change.	2023-01-20 20:42:30 -05:00
Geza Lore	599d23697d	IEEE compliant scheduler (#3384) ... This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278	2022-05-15 16:03:32 +01:00
Wilson Snyder	9821381059	Tests: new t_lint_latch_5 test (#2997).	2022-03-27 14:42:36 -04:00