Commit Graph

12 Commits

Author SHA1 Message Date
Wilson Snyder
6a5f77b278 Internals: Cleanup some string/model constructors. No functional change. 2022-08-29 23:50:32 -04:00
Yutetsu TAKATSUKASA
0658a7654f
Add tests of tracing SystemC model verilated with --hierarchical (#3252)
* Tests: Add t_hier_block_sc_trace(fst|vcd) that tests tracing hierarchical block on SystemC.

* Add a check that elaboration is done before a trace file is opened.

* Add a check that elaboration is done before trace() is called to verilated SystemC model.

* Tests: call sc_core::sc_start(sc_core::SC_ZERO_TIME) before opening a trace file

* Tests: Fix t_trace_two_sc to call sc_start before opening trace

* Use vl_fatal as suggested in PR review.
2021-12-23 08:41:11 +09:00
Geza Lore
1166728a8d Tests: make t_trace_*two* tests less sensitive to file names
No functional change intended
2021-07-19 17:48:41 +01:00
Geza Lore
708abe0dd1 Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.

Please see the updated documentation for the model interface changes.
2021-06-30 16:35:40 +01:00
Wilson Snyder
57d1404f40 Tests: Cleanup to return instead of exit 2021-02-25 19:26:36 -05:00
Wilson Snyder
0c328b6eaf clang-format of test_regress. No functional change. 2020-10-28 18:42:36 -04:00
Wilson Snyder
069eb97eca SystemC 2.3.0 or newer (SYSTEMC_VERSION >= 20111121) is now required. 2020-08-29 10:45:47 -04:00
Geza Lore
9d7086067c Rework serial/parallel build mode
Instead of __ALLfast.cpp and __ALLslow.cpp, we now create only a single
__ALL.cpp and compile it with OPT_FAST, this speeds up small builds
where the C compiler does not dominate. A separate patch will follow
turning VM_PARALLEL_BUILDS on by default at a certain size.

Given this change to the build there is now no point in emitting both
fast and slow routines into the same .cpp file when --output-split is
not set as they will be just included in the same __ALL.cpp file. To
keep things simpler and the output easier to comprehend, V3EmitC has
also been changed to always emit the fast and slow files separately.

Also change verilated.mk to apply OPT_SLOW to all slow files, not just
ones called *__Slow.cpp. This change in particular ensures __Syms.cpp
is build as slow.

Part of #2360.
2020-05-26 01:22:10 +01:00
Wilson Snyder
1ce360ed5b Add SPDX license identifiers. No functional change. 2020-03-21 11:24:24 -04:00
Wilson Snyder
30a33a6104 Add support for and , #2126. 2020-03-01 21:39:23 -05:00
Wilson Snyder
aac02acf92 Tests: Rename 2020-02-29 10:06:52 -05:00
Wilson Snyder
082c9e0b1d Tests: Add two-design trace tests. 2020-02-29 09:44:51 -05:00