10 Commits

Author	SHA1	Message	Date
Wilson Snyder	ede7236945	For --xml, add additional var information, bug1372.	2018-12-06 07:12:39 -05:00
Wilson Snyder	d396c55e34	In --xml-only show module_files and cells ala Verilog-Perl vhier, msg2716.	2018-11-01 19:53:26 -04:00
Wilson Snyder	14b48140bd	In --xml-only show the original unmodified names, msg2716.	2018-10-30 18:17:37 -04:00
Wilson Snyder	c29e7619eb	Tests: Support multiple scenario testing.	2018-05-07 20:42:28 -04:00
Wilson Snyder	2d580e6939	Support IEEE 1800-2017 as default language.	2018-03-12 22:26:34 -04:00
Wilson Snyder	b40b152b87	Fix missing edge type in xml output, msg2480.	2018-01-31 07:29:14 -05:00
Wilson Snyder	12607abb33	Remove tabs from --xml output.	2017-11-13 18:24:18 -05:00
Wilson Snyder	c0afe96b80	Fix addition of data types to --xml.	2017-11-09 18:04:16 -05:00
Wilson Snyder	33577eaa68	Tests: Less sensitivity to XML change	2012-04-29 08:23:24 -04:00
Wilson Snyder	204fb82975	Add very experimental --xml option	2012-03-20 16:13:10 -04:00