6 Commits

Author	SHA1	Message	Date
Geza Lore	599d23697d	IEEE compliant scheduler (#3384) ... This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278	2022-05-15 16:03:32 +01:00
Wilson Snyder	915ceb2d04	Tests: Untabify tests. No functional change.	2022-05-01 10:10:00 -04:00
Wilson Snyder	3a5cbd5b67	Internals: Untabify some embedded tabs.	2021-11-13 10:46:25 -05:00
Wilson Snyder	1ce360ed5b	Add SPDX license identifiers. No functional change.	2020-03-21 11:24:24 -04:00
Wilson Snyder	52912c6329	Convert repository to git from svn. ... - Change .cvsignore to .gitignore - Remove Id metacomments - Cleanup whitespace at end of lines	2008-06-09 21:25:10 -04:00
Wilson Snyder	ce10dbd11c	Version bump ... git-svn-id: file://localhost/svn/verilator/trunk/verilator@753 77ca24e4-aefa-0310-84f0-b9a241c72d87	2006-08-26 11:35:28 +00:00