github/verilator
1
0
Fork 1
mirror of https://github.com/verilator/verilator.git synced 2025-01-10 08:37:35 +00:00
Code Issues Packages Projects Releases Wiki Activity
1,556 Commits 2 Branches 161 Tags 124 MiB
2e10555f03
Commit Graph

3 Commits

Author SHA1 Message Date
Jeremy Bennett
de1bb5aeb6 Tests: fix driver.pl not tracing time 0, bug536. 
Signed-off-by: Wilson Snyder <wsnyder@wsnyder.org>
 2012-07-24 18:48:51 -04:00
Wilson Snyder
2dc7b7ad78 Tests: Use top. instead of TOP. to match other sims 2009-12-05 09:58:09 -05:00
Wilson Snyder
b1e6fe7139 Fix core dump with SystemVerilog var declarations under unnamed begins. 2009-10-11 20:50:31 -04:00