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Fix false WIDTHEXPAND on array declarations (#3959).

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This commit is contained in:
Wilson Snyder 2023-05-05 22:05:19 -04:00
parent 28944ed862
commit fdea386727
4 changed files with 46 additions and 3 deletions
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3
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@ -19,12 +19,13 @@ Verilator 5.011 devel
**Minor:**
* Optimize VPI callValueCbs (#4155). [Hennadii Chernyshchyk]
* Fix crash on duplicate imported modules (#3231). [Robert Balas]
* Fix false WIDTHEXPAND on array declarations (#3959). [JOTEGO]
* Fix marking overridden methods as coroutines (#4120) (#4169). [Krzysztof Bieganski, Antmicro Ltd]
* Fix duplicate static names in blocks in functions (#4144) (#4160). [Stefan Wallentowitz]
* Fix initialization order of initial static after function/task (#4159). [Kamil Rakoczy, Antmicro Ltd]
* Fix linking AstRefDType if it has parameterized class ref (#4164) (#4170). [Ryszard Rozak, Antmicro Ltd]
* Fix crash caused by $display() optimization (#4165) (#4166). [Tudor Timi]
* Fix crash on duplicate imported modules (#3231). [Robert Balas]
* Fix detection of wire/reg duplicates.

8
src/V3Width.cpp
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@ -1658,12 +1658,16 @@ private:
} else if (AstNodeDType* const keyp = VN_CAST(elementsp, NodeDType)) {
newp = new AstAssocArrayDType{nodep->fileline(), VFlagChildDType{}, childp, keyp};
} else {
// The subtract in the range may confuse users; as the array
// size is self determined there's no reason to warn about widths
FileLine* const elementsNewFl = elementsp->fileline();
elementsNewFl->warnOff(V3ErrorCode::WIDTHEXPAND, true);
// Must be expression that is constant, but we'll determine that later
newp = new AstUnpackArrayDType{
nodep->fileline(), VFlagChildDType{}, childp,
new AstRange{nodep->fileline(), new AstConst(elementsp->fileline(), 0),
new AstSub{elementsp->fileline(), VN_AS(elementsp, NodeExpr),
new AstConst(elementsp->fileline(), 1)}}};
new AstSub{elementsNewFl, VN_AS(elementsp, NodeExpr),
new AstConst(elementsNewFl, 1)}}};
}
nodep->replaceWith(newp);
VL_DO_DANGLING(nodep->deleteTree(), nodep);

17
test_regress/t/t_lint_width_arraydecl.pl Executable file
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@ -0,0 +1,17 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003-2009 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(vlt => 1);
lint(
);
ok(1);
1;

21
test_regress/t/t_lint_width_arraydecl.v Normal file
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@ -0,0 +1,21 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2009 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
localparam UADDR_WIDTH = 4'd10;
localparam UROM_WIDTH = 5'd17;
localparam UROM_DEPTH = 11'd1024;
module t(
input clk,
input [UADDR_WIDTH-1:0] mAddr,
output logic [UROM_WIDTH-1:0] mOutput);
reg [UROM_WIDTH-1:0] uRam[UROM_DEPTH];
always @(posedge clk) mOutput <= uRam[mAddr];
endmodule