From fdea386727cfa9ccfb1c421514bac2eab5bc491c Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Fri, 5 May 2023 22:05:19 -0400
Subject: [PATCH] Fix false WIDTHEXPAND on array declarations (#3959).

---
 Changes                                  |  3 ++-
 src/V3Width.cpp                          |  8 ++++++--
 test_regress/t/t_lint_width_arraydecl.pl | 17 +++++++++++++++++
 test_regress/t/t_lint_width_arraydecl.v  | 21 +++++++++++++++++++++
 4 files changed, 46 insertions(+), 3 deletions(-)
 create mode 100755 test_regress/t/t_lint_width_arraydecl.pl
 create mode 100644 test_regress/t/t_lint_width_arraydecl.v

diff --git a/Changes b/Changes
index e88a895d6..cd1c4dee6 100644
--- a/Changes
+++ b/Changes
@@ -19,12 +19,13 @@ Verilator 5.011 devel
 **Minor:**
 
 * Optimize VPI callValueCbs (#4155). [Hennadii Chernyshchyk]
+* Fix crash on duplicate imported modules (#3231). [Robert Balas]
+* Fix false WIDTHEXPAND on array declarations (#3959). [JOTEGO]
 * Fix marking overridden methods as coroutines (#4120) (#4169). [Krzysztof Bieganski, Antmicro Ltd]
 * Fix duplicate static names in blocks in functions (#4144) (#4160). [Stefan Wallentowitz]
 * Fix initialization order of initial static after function/task (#4159). [Kamil Rakoczy, Antmicro Ltd]
 * Fix linking AstRefDType if it has parameterized class ref (#4164) (#4170). [Ryszard Rozak, Antmicro Ltd]
 * Fix crash caused by $display() optimization (#4165) (#4166). [Tudor Timi]
-* Fix crash on duplicate imported modules (#3231). [Robert Balas]
 * Fix detection of wire/reg duplicates.
 
 
diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index 50c7c9af7..0d02e36a0 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -1658,12 +1658,16 @@ private:
         } else if (AstNodeDType* const keyp = VN_CAST(elementsp, NodeDType)) {
             newp = new AstAssocArrayDType{nodep->fileline(), VFlagChildDType{}, childp, keyp};
         } else {
+            // The subtract in the range may confuse users; as the array
+            // size is self determined there's no reason to warn about widths
+            FileLine* const elementsNewFl = elementsp->fileline();
+            elementsNewFl->warnOff(V3ErrorCode::WIDTHEXPAND, true);
             // Must be expression that is constant, but we'll determine that later
             newp = new AstUnpackArrayDType{
                 nodep->fileline(), VFlagChildDType{}, childp,
                 new AstRange{nodep->fileline(), new AstConst(elementsp->fileline(), 0),
-                             new AstSub{elementsp->fileline(), VN_AS(elementsp, NodeExpr),
-                                        new AstConst(elementsp->fileline(), 1)}}};
+                             new AstSub{elementsNewFl, VN_AS(elementsp, NodeExpr),
+                                        new AstConst(elementsNewFl, 1)}}};
         }
         nodep->replaceWith(newp);
         VL_DO_DANGLING(nodep->deleteTree(), nodep);
diff --git a/test_regress/t/t_lint_width_arraydecl.pl b/test_regress/t/t_lint_width_arraydecl.pl
new file mode 100755
index 000000000..629a44bbb
--- /dev/null
+++ b/test_regress/t/t_lint_width_arraydecl.pl
@@ -0,0 +1,17 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2009 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt => 1);
+
+lint(
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_lint_width_arraydecl.v b/test_regress/t/t_lint_width_arraydecl.v
new file mode 100644
index 000000000..5de0ecc50
--- /dev/null
+++ b/test_regress/t/t_lint_width_arraydecl.v
@@ -0,0 +1,21 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2009 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+localparam UADDR_WIDTH = 4'd10;
+localparam UROM_WIDTH = 5'd17;
+localparam UROM_DEPTH = 11'd1024;
+
+
+module t(
+         input clk,
+         input [UADDR_WIDTH-1:0] mAddr,
+         output logic [UROM_WIDTH-1:0] mOutput);
+
+   reg [UROM_WIDTH-1:0] uRam[UROM_DEPTH];
+
+   always @(posedge clk) mOutput <= uRam[mAddr];
+
+endmodule