Fix insertion at queue's end (#4619)

Signed-off-by: Krzysztof Boronski <kboronski@antmicro.com>
Co-authored-by: Wilson Snyder <wsnyder@wsnyder.org>
This commit is contained in:
Krzysztof Boroński 2023-10-25 17:41:28 +02:00 committed by GitHub
parent cf6e362972
commit f91259f46d
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3 changed files with 45 additions and 1 deletions

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@ -545,7 +545,7 @@ public:
// function void q.insert(index, value);
void insert(int32_t index, const T_Value& value) {
if (VL_UNLIKELY(index < 0 || index >= m_deque.size())) return;
if (VL_UNLIKELY(index < 0 || index > m_deque.size())) return;
m_deque.insert(m_deque.begin() + index, value);
}

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@ -0,0 +1,21 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2023 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(simulator => 1);
compile(
);
execute(
check_finished => 1,
);
ok(1);
1;

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@ -0,0 +1,23 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2023 by Antmicro Ltd.
// SPDX-License-Identifier: CC0-1.0
module t();
initial begin
int queue[$];
queue.insert(0, 0);
if (queue.size() != 1) $stop;
queue.insert(1, 1);
if (queue.size() != 2) $stop;
if (queue[0] != 0) $stop;
if (queue[1] != 1) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule