From f91259f46d33f972a5b9df3ef1b971fe15b4b9aa Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Krzysztof=20Boro=C5=84ski?=
 <94375110+kboronski-ant@users.noreply.github.com>
Date: Wed, 25 Oct 2023 17:41:28 +0200
Subject: [PATCH] Fix insertion at queue's end (#4619)

Signed-off-by: Krzysztof Boronski <kboronski@antmicro.com>
Co-authored-by: Wilson Snyder <wsnyder@wsnyder.org>
---
 include/verilated_types.h               |  2 +-
 test_regress/t/t_queue_insert_at_end.pl | 21 +++++++++++++++++++++
 test_regress/t/t_queue_insert_at_end.v  | 23 +++++++++++++++++++++++
 3 files changed, 45 insertions(+), 1 deletion(-)
 create mode 100755 test_regress/t/t_queue_insert_at_end.pl
 create mode 100644 test_regress/t/t_queue_insert_at_end.v

diff --git a/include/verilated_types.h b/include/verilated_types.h
index 4dd4505d4..0f9ea4a02 100644
--- a/include/verilated_types.h
+++ b/include/verilated_types.h
@@ -545,7 +545,7 @@ public:
 
     // function void q.insert(index, value);
     void insert(int32_t index, const T_Value& value) {
-        if (VL_UNLIKELY(index < 0 || index >= m_deque.size())) return;
+        if (VL_UNLIKELY(index < 0 || index > m_deque.size())) return;
         m_deque.insert(m_deque.begin() + index, value);
     }
 
diff --git a/test_regress/t/t_queue_insert_at_end.pl b/test_regress/t/t_queue_insert_at_end.pl
new file mode 100755
index 000000000..859050d63
--- /dev/null
+++ b/test_regress/t/t_queue_insert_at_end.pl
@@ -0,0 +1,21 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2023 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_queue_insert_at_end.v b/test_regress/t/t_queue_insert_at_end.v
new file mode 100644
index 000000000..6ed3c006f
--- /dev/null
+++ b/test_regress/t/t_queue_insert_at_end.v
@@ -0,0 +1,23 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2023 by Antmicro Ltd.
+// SPDX-License-Identifier: CC0-1.0
+
+module t();
+  initial begin
+    int queue[$];
+
+    queue.insert(0, 0);
+    if (queue.size() != 1) $stop;
+
+    queue.insert(1, 1);
+    if (queue.size() != 2) $stop;
+
+    if (queue[0] != 0) $stop;
+    if (queue[1] != 1) $stop;
+
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
+endmodule