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Tests: Fix coverage holes. No functional change.
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Wilson Snyder
parent
bdceb08963
commit
f55177a49f
@ -16,8 +16,8 @@ module t (/*AUTOARG*/
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reg [31:0] b;
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wire [2:0] bf; buf BF0 (bf[0], a[0]),
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BF1 (bf[1], a[1]),
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BF2 (bf[2], a[2]);
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BF1 (bf[1], a[1]),
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BF2 (bf[2], a[2]);
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// verilator lint_off IMPLICIT
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not #(0.108) NT0 (nt0, a[0]);
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@ -48,43 +48,66 @@ module t (/*AUTOARG*/
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// path delays
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(A1 *> Q) = (a$A1$Y, a$A1$Y);
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(A0 *> Q) = (b$A0$Y, a$A0$Z);
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if (C1) (IN => OUT) = (1,1);
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ifnone (IN => OUT) = (2,2);
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showcancelled Q;
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noshowcancelled Q;
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pulsestyle_ondetect Q;
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pulsestyle_onevent Q;
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// other unimplemented stuff
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$fullskew();
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$hold();
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$nochange();
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$period();
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$recovery();
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$recrem();
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$removal();
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$setup();
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$setuphold();
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$skew();
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$timeskew();
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$width();
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endspecify
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`endif
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always @ (posedge clk) begin
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if (cyc!=0) begin
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cyc <= cyc + 1;
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if (cyc==1) begin
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a <= 32'h18f6b034;
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b <= 32'h834bf892;
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end
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if (cyc==2) begin
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a <= 32'h529ab56f;
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b <= 32'h7835a237;
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if (bf !== 3'b100) $stop;
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if (nt0 !== 1'b1) $stop;
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if (an0 !== 1'b0) $stop;
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if (nd0 !== 1'b1) $stop;
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if (or0 !== 1'b0) $stop;
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if (nr0 !== 1'b1) $stop;
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if (xo0 !== 1'b0) $stop;
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if (xn0 !== 1'b1) $stop;
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if (ba != 32'h18f6b034) $stop;
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end
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if (cyc==3) begin
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if (bf !== 3'b111) $stop;
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if (nt0 !== 1'b0) $stop;
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if (an0 !== 1'b1) $stop;
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if (nd0 !== 1'b0) $stop;
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if (or0 !== 1'b1) $stop;
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if (nr0 !== 1'b0) $stop;
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if (xo0 !== 1'b0) $stop;
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if (xn0 !== 1'b0) $stop;
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end
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if (cyc==4) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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cyc <= cyc + 1;
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if (cyc==1) begin
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a <= 32'h18f6b034;
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b <= 32'h834bf892;
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end
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if (cyc==2) begin
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a <= 32'h529ab56f;
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b <= 32'h7835a237;
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if (bf !== 3'b100) $stop;
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if (nt0 !== 1'b1) $stop;
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if (an0 !== 1'b0) $stop;
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if (nd0 !== 1'b1) $stop;
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if (or0 !== 1'b0) $stop;
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if (nr0 !== 1'b1) $stop;
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if (xo0 !== 1'b0) $stop;
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if (xn0 !== 1'b1) $stop;
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if (ba != 32'h18f6b034) $stop;
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end
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if (cyc==3) begin
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if (bf !== 3'b111) $stop;
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if (nt0 !== 1'b0) $stop;
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if (an0 !== 1'b1) $stop;
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if (nd0 !== 1'b0) $stop;
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if (or0 !== 1'b1) $stop;
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if (nr0 !== 1'b0) $stop;
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if (xo0 !== 1'b0) $stop;
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if (xn0 !== 1'b0) $stop;
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end
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if (cyc==4) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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18
test_regress/t/t_gate_strength.pl
Executable file
18
test_regress/t/t_gate_strength.pl
Executable file
@ -0,0 +1,18 @@
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2004 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(simulator => 1);
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compile(
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verilator_flags2 => ['-bbox-unsup'],
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);
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ok(1);
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1;
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75
test_regress/t/t_gate_strength.v
Normal file
75
test_regress/t/t_gate_strength.v
Normal file
@ -0,0 +1,75 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2004 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc; initial cyc=1;
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logic [31:0] a;
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// verilator lint_off IMPLICIT
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assign (highz0, supply1) nt00 = a[0];
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assign (supply0, highz1) nt01 = a[0];
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assign (supply0, supply1) nt02 = a[0];
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assign (strong0, strong1) nt03 = a[0];
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assign (pull0, pull1) nt04 = a[0];
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assign (weak0, weak1) nt05 = a[0];
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assign (highz0, supply1) nt10 = a[0];
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assign (supply0, highz1) nt11 = a[0];
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assign (supply0, supply1) nt12 = a[0];
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assign (strong0, strong1) nt13 = a[0];
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assign (pull0, pull1) nt14 = a[0];
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assign (weak0, weak1) nt15 = a[0];
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// verilator lint_on IMPLICIT
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always @ (posedge clk) begin
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if (cyc!=0) begin
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cyc <= cyc + 1;
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if (cyc==1) begin
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a <= 32'h18f6b030;
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end
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if (cyc==2) begin
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a <= 32'h18f6b03f;
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if (nt00 !== 1'b0) $stop;
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if (nt01 !== 1'b0) $stop;
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if (nt02 !== 1'b0) $stop;
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if (nt03 !== 1'b0) $stop;
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if (nt04 !== 1'b0) $stop;
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if (nt05 !== 1'b0) $stop;
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if (nt10 !== 1'b0) $stop;
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if (nt11 !== 1'b0) $stop;
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if (nt12 !== 1'b0) $stop;
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if (nt13 !== 1'b0) $stop;
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if (nt14 !== 1'b0) $stop;
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if (nt15 !== 1'b0) $stop;
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end
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if (cyc==3) begin
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if (nt00 !== 1'b1) $stop;
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if (nt01 !== 1'b1) $stop;
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if (nt02 !== 1'b1) $stop;
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if (nt03 !== 1'b1) $stop;
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if (nt04 !== 1'b1) $stop;
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if (nt05 !== 1'b1) $stop;
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if (nt10 !== 1'b1) $stop;
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if (nt11 !== 1'b1) $stop;
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if (nt12 !== 1'b1) $stop;
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if (nt13 !== 1'b1) $stop;
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if (nt14 !== 1'b1) $stop;
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if (nt15 !== 1'b1) $stop;
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end
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if (cyc==4) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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@ -15,9 +15,9 @@ module t (/*AUTOARG*/
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task check (integer line, real got, real expec);
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real delta;
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delta = got-expec;
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if (delta > 0.001) begin
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$display("Line%d: Got %g Exp %g\n", line, got, expec);
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$stop;
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if (delta > 0.001 || delta < -0.001) begin
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$write("Line%0d: Got %g Exp %g\n", line, got, expec);
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$stop;
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end
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endtask
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@ -27,21 +27,30 @@ module t (/*AUTOARG*/
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sub sub (.*);
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initial begin
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check(`__LINE__, sqrt(2.0) , 1.414);
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check(`__LINE__, pow(2.0,2.0) , 4.0);
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check(`__LINE__, ln(2.0) , 0.693147);
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check(`__LINE__, log(2.0) , 0.30103);
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check(`__LINE__, floor(2.5) , 2.0);
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check(`__LINE__, exp(2.0) , 7.38906);
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check(`__LINE__, ceil(2.5) , 3.0);
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check(`__LINE__, atan(0.5) , 0.463648);
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check(`__LINE__, atan2(0.5, 0.3) , 1.03038);
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check(`__LINE__, atanh(0.5) , 0.549306);
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check(`__LINE__, ceil(2.5) , 3.0);
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check(`__LINE__, cos(0.5) , 0.877583);
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check(`__LINE__, cosh(0.5) , 1.12763);
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check(`__LINE__, exp(2.0) , 7.38906);
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check(`__LINE__, floor(2.5) , 2.0);
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check(`__LINE__, ln(2.0) , 0.693147);
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check(`__LINE__, log(2.0) , 0.30103);
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check(`__LINE__, pow(2.0,2.0) , 4.0);
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check(`__LINE__, sin(0.5) , 0.479426);
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check(`__LINE__, sinh(0.5) , 0.521095);
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check(`__LINE__, sqrt(2.0) , 1.414);
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check(`__LINE__, tan(0.5) , 0.546302);
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check(`__LINE__, tanh(0.5) , 0.462117);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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module sub (
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input wreal wr
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);
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input wreal wr
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);
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initial begin
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if (wr != 1.1) $stop;
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end
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