From f55177a49f793c93e5a7b805c300d94a05ca03f3 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sat, 10 Jul 2021 07:11:50 -0400 Subject: [PATCH] Tests: Fix coverage holes. No functional change. --- test_regress/t/t_gate_basic.v | 91 +++++++++++++++++++------------ test_regress/t/t_gate_strength.pl | 18 ++++++ test_regress/t/t_gate_strength.v | 75 +++++++++++++++++++++++++ test_regress/t/t_vams_basic.v | 33 +++++++---- 4 files changed, 171 insertions(+), 46 deletions(-) create mode 100755 test_regress/t/t_gate_strength.pl create mode 100644 test_regress/t/t_gate_strength.v diff --git a/test_regress/t/t_gate_basic.v b/test_regress/t/t_gate_basic.v index 8f120463a..9a3e7fbab 100644 --- a/test_regress/t/t_gate_basic.v +++ b/test_regress/t/t_gate_basic.v @@ -16,8 +16,8 @@ module t (/*AUTOARG*/ reg [31:0] b; wire [2:0] bf; buf BF0 (bf[0], a[0]), - BF1 (bf[1], a[1]), - BF2 (bf[2], a[2]); + BF1 (bf[1], a[1]), + BF2 (bf[2], a[2]); // verilator lint_off IMPLICIT not #(0.108) NT0 (nt0, a[0]); @@ -48,43 +48,66 @@ module t (/*AUTOARG*/ // path delays (A1 *> Q) = (a$A1$Y, a$A1$Y); (A0 *> Q) = (b$A0$Y, a$A0$Z); + + if (C1) (IN => OUT) = (1,1); + ifnone (IN => OUT) = (2,2); + + showcancelled Q; + noshowcancelled Q; + pulsestyle_ondetect Q; + pulsestyle_onevent Q; + + // other unimplemented stuff + $fullskew(); + $hold(); + $nochange(); + $period(); + $recovery(); + $recrem(); + $removal(); + $setup(); + $setuphold(); + $skew(); + $timeskew(); + $width(); + endspecify `endif always @ (posedge clk) begin if (cyc!=0) begin - cyc <= cyc + 1; - if (cyc==1) begin - a <= 32'h18f6b034; - b <= 32'h834bf892; - end - if (cyc==2) begin - a <= 32'h529ab56f; - b <= 32'h7835a237; - if (bf !== 3'b100) $stop; - if (nt0 !== 1'b1) $stop; - if (an0 !== 1'b0) $stop; - if (nd0 !== 1'b1) $stop; - if (or0 !== 1'b0) $stop; - if (nr0 !== 1'b1) $stop; - if (xo0 !== 1'b0) $stop; - if (xn0 !== 1'b1) $stop; - if (ba != 32'h18f6b034) $stop; - end - if (cyc==3) begin - if (bf !== 3'b111) $stop; - if (nt0 !== 1'b0) $stop; - if (an0 !== 1'b1) $stop; - if (nd0 !== 1'b0) $stop; - if (or0 !== 1'b1) $stop; - if (nr0 !== 1'b0) $stop; - if (xo0 !== 1'b0) $stop; - if (xn0 !== 1'b0) $stop; - end - if (cyc==4) begin - $write("*-* All Finished *-*\n"); - $finish; - end + cyc <= cyc + 1; + if (cyc==1) begin + a <= 32'h18f6b034; + b <= 32'h834bf892; + end + if (cyc==2) begin + a <= 32'h529ab56f; + b <= 32'h7835a237; + if (bf !== 3'b100) $stop; + if (nt0 !== 1'b1) $stop; + if (an0 !== 1'b0) $stop; + if (nd0 !== 1'b1) $stop; + if (or0 !== 1'b0) $stop; + if (nr0 !== 1'b1) $stop; + if (xo0 !== 1'b0) $stop; + if (xn0 !== 1'b1) $stop; + if (ba != 32'h18f6b034) $stop; + end + if (cyc==3) begin + if (bf !== 3'b111) $stop; + if (nt0 !== 1'b0) $stop; + if (an0 !== 1'b1) $stop; + if (nd0 !== 1'b0) $stop; + if (or0 !== 1'b1) $stop; + if (nr0 !== 1'b0) $stop; + if (xo0 !== 1'b0) $stop; + if (xn0 !== 1'b0) $stop; + end + if (cyc==4) begin + $write("*-* All Finished *-*\n"); + $finish; + end end end diff --git a/test_regress/t/t_gate_strength.pl b/test_regress/t/t_gate_strength.pl new file mode 100755 index 000000000..dd8b670e0 --- /dev/null +++ b/test_regress/t/t_gate_strength.pl @@ -0,0 +1,18 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2004 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + verilator_flags2 => ['-bbox-unsup'], + ); + +ok(1); +1; diff --git a/test_regress/t/t_gate_strength.v b/test_regress/t/t_gate_strength.v new file mode 100644 index 000000000..038ca9cfb --- /dev/null +++ b/test_regress/t/t_gate_strength.v @@ -0,0 +1,75 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2004 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=1; + + logic [31:0] a; + + // verilator lint_off IMPLICIT + assign (highz0, supply1) nt00 = a[0]; + assign (supply0, highz1) nt01 = a[0]; + assign (supply0, supply1) nt02 = a[0]; + assign (strong0, strong1) nt03 = a[0]; + assign (pull0, pull1) nt04 = a[0]; + assign (weak0, weak1) nt05 = a[0]; + + assign (highz0, supply1) nt10 = a[0]; + assign (supply0, highz1) nt11 = a[0]; + assign (supply0, supply1) nt12 = a[0]; + assign (strong0, strong1) nt13 = a[0]; + assign (pull0, pull1) nt14 = a[0]; + assign (weak0, weak1) nt15 = a[0]; + // verilator lint_on IMPLICIT + + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + if (cyc==1) begin + a <= 32'h18f6b030; + end + if (cyc==2) begin + a <= 32'h18f6b03f; + if (nt00 !== 1'b0) $stop; + if (nt01 !== 1'b0) $stop; + if (nt02 !== 1'b0) $stop; + if (nt03 !== 1'b0) $stop; + if (nt04 !== 1'b0) $stop; + if (nt05 !== 1'b0) $stop; + if (nt10 !== 1'b0) $stop; + if (nt11 !== 1'b0) $stop; + if (nt12 !== 1'b0) $stop; + if (nt13 !== 1'b0) $stop; + if (nt14 !== 1'b0) $stop; + if (nt15 !== 1'b0) $stop; + end + if (cyc==3) begin + if (nt00 !== 1'b1) $stop; + if (nt01 !== 1'b1) $stop; + if (nt02 !== 1'b1) $stop; + if (nt03 !== 1'b1) $stop; + if (nt04 !== 1'b1) $stop; + if (nt05 !== 1'b1) $stop; + if (nt10 !== 1'b1) $stop; + if (nt11 !== 1'b1) $stop; + if (nt12 !== 1'b1) $stop; + if (nt13 !== 1'b1) $stop; + if (nt14 !== 1'b1) $stop; + if (nt15 !== 1'b1) $stop; + end + if (cyc==4) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + +endmodule diff --git a/test_regress/t/t_vams_basic.v b/test_regress/t/t_vams_basic.v index c658d64e2..8a71bfe42 100644 --- a/test_regress/t/t_vams_basic.v +++ b/test_regress/t/t_vams_basic.v @@ -15,9 +15,9 @@ module t (/*AUTOARG*/ task check (integer line, real got, real expec); real delta; delta = got-expec; - if (delta > 0.001) begin - $display("Line%d: Got %g Exp %g\n", line, got, expec); - $stop; + if (delta > 0.001 || delta < -0.001) begin + $write("Line%0d: Got %g Exp %g\n", line, got, expec); + $stop; end endtask @@ -27,21 +27,30 @@ module t (/*AUTOARG*/ sub sub (.*); initial begin - check(`__LINE__, sqrt(2.0) , 1.414); - check(`__LINE__, pow(2.0,2.0) , 4.0); - check(`__LINE__, ln(2.0) , 0.693147); - check(`__LINE__, log(2.0) , 0.30103); - check(`__LINE__, floor(2.5) , 2.0); - check(`__LINE__, exp(2.0) , 7.38906); - check(`__LINE__, ceil(2.5) , 3.0); + check(`__LINE__, atan(0.5) , 0.463648); + check(`__LINE__, atan2(0.5, 0.3) , 1.03038); + check(`__LINE__, atanh(0.5) , 0.549306); + check(`__LINE__, ceil(2.5) , 3.0); + check(`__LINE__, cos(0.5) , 0.877583); + check(`__LINE__, cosh(0.5) , 1.12763); + check(`__LINE__, exp(2.0) , 7.38906); + check(`__LINE__, floor(2.5) , 2.0); + check(`__LINE__, ln(2.0) , 0.693147); + check(`__LINE__, log(2.0) , 0.30103); + check(`__LINE__, pow(2.0,2.0) , 4.0); + check(`__LINE__, sin(0.5) , 0.479426); + check(`__LINE__, sinh(0.5) , 0.521095); + check(`__LINE__, sqrt(2.0) , 1.414); + check(`__LINE__, tan(0.5) , 0.546302); + check(`__LINE__, tanh(0.5) , 0.462117); $write("*-* All Finished *-*\n"); $finish; end endmodule module sub ( - input wreal wr - ); + input wreal wr + ); initial begin if (wr != 1.1) $stop; end