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Fix this
in member initialization (#4710).
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Changes
@ -25,6 +25,7 @@ Verilator 5.021 devel
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* Support SystemC 3.0.0 public review version (#4805) (#4807). [Anthony Donlon]
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* Support SystemC 3.0.0 public review version (#4805) (#4807). [Anthony Donlon]
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* Support parsing anonymous primitive instantiations (#4809). [Anthony Donlon]
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* Support parsing anonymous primitive instantiations (#4809). [Anthony Donlon]
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* Fix to not emit already waived warnings in waiver output (#4574) (#4818). [Jonathan Schröter]
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* Fix to not emit already waived warnings in waiver output (#4574) (#4818). [Jonathan Schröter]
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* Fix `this` in member initialization (#4710). [eliasphanna]
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* Fix localparam elaboration (#3858) (#4794). [Andrew Nolte]
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* Fix localparam elaboration (#3858) (#4794). [Andrew Nolte]
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* Fix lint_off disables on preprocessor warnings (#4703). [Srinivasan Venkataramanan]
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* Fix lint_off disables on preprocessor warnings (#4703). [Srinivasan Venkataramanan]
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* Fix $time not rounding up (#4790) (#4792). [Paul Wright]
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* Fix $time not rounding up (#4790) (#4792). [Paul Wright]
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@ -2208,9 +2208,9 @@ class LinkDotResolveVisitor final : public VNVisitor {
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}
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}
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VSymEnt* getThisClassSymp() {
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VSymEnt* getThisClassSymp() {
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VSymEnt* classSymp = m_ds.m_dotSymp;
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VSymEnt* classSymp = m_ds.m_dotSymp;
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do {
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while (classSymp && !VN_IS(classSymp->nodep(), Class)) {
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classSymp = classSymp->parentp();
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classSymp = classSymp->parentp();
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} while (classSymp && !VN_IS(classSymp->nodep(), Class));
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}
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return classSymp;
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return classSymp;
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}
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}
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void importImplementsClass(AstClass* implementsClassp, VSymEnt* interfaceSymp,
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void importImplementsClass(AstClass* implementsClassp, VSymEnt* interfaceSymp,
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21
test_regress/t/t_0.pl
Executable file
21
test_regress/t/t_0.pl
Executable file
@ -0,0 +1,21 @@
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2024 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(simulator => 1);
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compile(
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);
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execute(
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check_finished => 1,
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);
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ok(1);
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1;
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37
test_regress/t/t_0.v
Normal file
37
test_regress/t/t_0.v
Normal file
@ -0,0 +1,37 @@
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// DESCRIPTION: Verilator: Verilog Test module
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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interface class ICls;
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pure virtual function string get();
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endclass
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class Cls;
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string name;
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ICls icls;
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function new(string name, ICls icls);
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this.name = name;
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this.icls = icls;
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endfunction
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endclass
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class Testcase implements ICls;
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Cls cls = new("test_class", this);
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virtual function string get();
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return "In ICls";
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endfunction
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endclass
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module t(/*AUTOARG*/);
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initial begin
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Testcase test;
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test = new;
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if (test.cls.name != "test_class") $stop;
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if (test.cls.icls.get() != "In ICls") $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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