From f13f2296de1fa23298392a4e32f0321f8c62a7ba Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sun, 4 Feb 2024 16:09:01 -0500 Subject: [PATCH] Fix `this` in member initialization (#4710). --- Changes | 1 + src/V3LinkDot.cpp | 4 ++-- test_regress/t/t_0.pl | 21 +++++++++++++++++++++ test_regress/t/t_0.v | 37 +++++++++++++++++++++++++++++++++++++ 4 files changed, 61 insertions(+), 2 deletions(-) create mode 100755 test_regress/t/t_0.pl create mode 100644 test_regress/t/t_0.v diff --git a/Changes b/Changes index 95f7afa2e..a8bddc209 100644 --- a/Changes +++ b/Changes @@ -25,6 +25,7 @@ Verilator 5.021 devel * Support SystemC 3.0.0 public review version (#4805) (#4807). [Anthony Donlon] * Support parsing anonymous primitive instantiations (#4809). [Anthony Donlon] * Fix to not emit already waived warnings in waiver output (#4574) (#4818). [Jonathan Schröter] +* Fix `this` in member initialization (#4710). [eliasphanna] * Fix localparam elaboration (#3858) (#4794). [Andrew Nolte] * Fix lint_off disables on preprocessor warnings (#4703). [Srinivasan Venkataramanan] * Fix $time not rounding up (#4790) (#4792). [Paul Wright] diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp index a8f6a58a7..f6eb6fe06 100644 --- a/src/V3LinkDot.cpp +++ b/src/V3LinkDot.cpp @@ -2208,9 +2208,9 @@ class LinkDotResolveVisitor final : public VNVisitor { } VSymEnt* getThisClassSymp() { VSymEnt* classSymp = m_ds.m_dotSymp; - do { + while (classSymp && !VN_IS(classSymp->nodep(), Class)) { classSymp = classSymp->parentp(); - } while (classSymp && !VN_IS(classSymp->nodep(), Class)); + } return classSymp; } void importImplementsClass(AstClass* implementsClassp, VSymEnt* interfaceSymp, diff --git a/test_regress/t/t_0.pl b/test_regress/t/t_0.pl new file mode 100755 index 000000000..e64ab41be --- /dev/null +++ b/test_regress/t/t_0.pl @@ -0,0 +1,21 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + ); + +execute( + check_finished => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_0.v b/test_regress/t/t_0.v new file mode 100644 index 000000000..81a33cba0 --- /dev/null +++ b/test_regress/t/t_0.v @@ -0,0 +1,37 @@ +// DESCRIPTION: Verilator: Verilog Test module +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2024 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +interface class ICls; + pure virtual function string get(); +endclass + +class Cls; + string name; + ICls icls; + function new(string name, ICls icls); + this.name = name; + this.icls = icls; + endfunction +endclass + +class Testcase implements ICls; + Cls cls = new("test_class", this); + virtual function string get(); + return "In ICls"; + endfunction +endclass + +module t(/*AUTOARG*/); + + initial begin + Testcase test; + test = new; + if (test.cls.name != "test_class") $stop; + if (test.cls.icls.get() != "In ICls") $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule