Tests: Misc test cleanups from Python branch.

include/verilated.cpp

@@ -3002,7 +3002,7 @@ const VerilatedScopeNameMap* VerilatedContext::scopeNameMap() VL_MT_SAFE {
 //======================================================================
 // VerilatedContext:: Methods - trace
 
-void VerilatedContext::trace(VerilatedTraceBaseC* tfp, int levels, int options) VL_MT_SAFE {
+void VerilatedContext::trace(VerilatedTraceBaseC* tfp, int levels, int options) {
     VL_DEBUG_IF(VL_DBG_MSGF("+ VerilatedContext::trace\n"););
     if (tfp->isOpen()) {
         VL_FATAL_MT("", 0, "",

test_regress/t/t_flag_lib_dpi.pl

@@ -2,9 +2,11 @@
 if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# This file ONLY is placed under the Creative Commons Public Domain, for
-# any use, without warranty, 2023 by Shupei Fan.
-# SPDX-License-Identifier: CC0-1.0
+# Copyright 2023 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 scenarios(vlt => 1);
 

test_regress/t/t_pipe_exit_bad.pl

@@ -13,11 +13,11 @@ scenarios(vlt => 1);
 top_filename("t/t_pipe_filter.v");
 
 lint(
-    verilator_flags2 => ['-E --pipe-filter \'python3 t/t_pipe_exit_bad.pf\' '],
+    verilator_flags2 => ['-E --pipe-filter \'python3 t/t_pipe_exit_bad_pf.pf\' '],
     stdout_filename => $stdout_filename,
     fails => 1,
     expect =>
-'%Error: t_pipe_exit_bad.pf: Intentional bad exit status....*',
+'%Error: t_pipe_exit_bad_pf.pf: Intentional bad exit status....*',
     );
 ok(1);
 

test_regress/t/t_pipe_exit_bad_pf.pf

@@ -11,4 +11,4 @@
 
 import sys
 
-sys.exit("%Error: t_pipe_exit_bad.pf: Intentional bad exit status...")
+sys.exit("%Error: t_pipe_exit_bad_pf.pf: Intentional bad exit status...")

test_regress/t/t_pipe_filter.pl

@@ -13,7 +13,7 @@ scenarios(vlt => 1);
 my $stdout_filename = "$Self->{obj_dir}/$Self->{name}__test.vpp";
 
 compile(
-    verilator_flags2 => ['-E --pipe-filter \'python3 t/t_pipe_filter.pf\' '],
+    verilator_flags2 => ['-E --pipe-filter \'python3 t/t_pipe_filter_pf.pf\' '],
     verilator_make_gmake => 0,
     make_top_shell => 0,
     make_main => 0,

test_regress/t/t_pipe_filter_pf.pf

@@ -15,11 +15,11 @@ import sys
 Debug = False
 
 if Debug:
-    sys.stderr.write("t_pipe_filter.pf: Hello from t_pipe_filter.pf\n")
+    sys.stderr.write("t_pipe_filter_pf.pf: Hello from t_pipe_filter_pf.pf\n")
 
 for cmd in sys.stdin:
     if Debug:
-        sys.stderr.write("t_pipe_filter.pf: gotcmd: " + cmd)
+        sys.stderr.write("t_pipe_filter_pf.pf: gotcmd: " + cmd)
 
     match = re.match(r'read "(.*)"', cmd)
     if match:
@@ -53,9 +53,9 @@ for cmd in sys.stdin:
         print("Content-Length: " + str(len(wholefile)) + "\n" + wholefile)
         sys.stdout.flush()
     else:
-        sys.exit("t_pipe_filter.pf: %Error: Unknown command: " + cmd)
+        sys.exit("t_pipe_filter_pf.pf: %Error: Unknown command: " + cmd)
 
 if Debug:
-    sys.stderr.write("t_pipe_filter.pf: Fin\n")
+    sys.stderr.write("t_pipe_filter_pf.pf: Fin\n")
 
 sys.exit(0)

test_regress/t/t_trace_dumpvars_dyn_fst_1.out

@@ -15,6 +15,12 @@ $scope module sub1a $end
 $var parameter 32 " ADD [31:0] $end
 $var wire 32 ! cyc [31:0] $end
 $var wire 32 # value [31:0] $end
+$scope module sub2a $end
+$upscope $end
+$scope module sub2b $end
+$upscope $end
+$scope module sub2c $end
+$upscope $end
 $upscope $end
 $scope module sub1b $end
 $var parameter 32 $ ADD [31:0] $end

test_regress/t/t_trace_dumpvars_dyn_vcd_1.out

@@ -1,7 +1,5 @@
 $version Generated by VerilatedVcd $end
-$date Sat Mar  5 13:47:52 2022 $end
 $timescale 1ps $end
-
  $scope module top $end
   $scope module t $end
    $var wire 32 # cyc [31:0] $end
@@ -9,6 +7,12 @@ $timescale 1ps $end
     $var wire 32 - ADD [31:0] $end
     $var wire 32 # cyc [31:0] $end
     $var wire 32 $ value [31:0] $end
+    $scope module sub2a $end
+    $upscope $end
+    $scope module sub2b $end
+    $upscope $end
+    $scope module sub2c $end
+    $upscope $end
    $upscope $end
    $scope module sub1b $end
     $var wire 32 1 ADD [31:0] $end

test_regress/t/t_trace_param_override.out

@@ -1,11 +1,9 @@
 $version Generated by VerilatedVcd $end
-$date Thu Nov 10 19:19:51 2022 $end
 $timescale 1ps $end
-
  $scope module TOP $end
   $scope module t $end
-   $var wire 32 $ PORIG [31:0] $end
    $var wire 32 # POVERRODE [31:0] $end
+   $var wire 32 $ PORIG [31:0] $end
   $upscope $end
  $upscope $end
 $enddefinitions $end

test_regress/t/t_wrapper_clone.pl

@@ -2,9 +2,11 @@
 if (!$::Driver) { use strict; use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test module for prepareClone/atClone APIs
 #
-# This file ONLY is placed into the Public Domain, for any use,
-# without warranty, 2023 by Yinan Xu.
-# SPDX-License-Identifier: CC0-1.0
+# Copyright 2021 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 scenarios(vlt_all => 1);