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Fix parametrized defines with empty arguments.

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This commit is contained in:
Wilson Snyder 2010-02-21 07:20:39 -05:00
parent 72218fb475
commit e39eddf3fe
3 changed files with 6 additions and 1 deletions
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2
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@ -11,6 +11,8 @@ indicates the contributor was also the author of the fix; Thanks!
**** Fix make uninstall, bug216. [Iztok Jeras]
**** Fix parametrized defines with empty arguments.
* Verilator 3.800 2010/02/07
Application visible changes:

4
src/V3PreProc.cpp
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@ -511,7 +511,9 @@ string V3PreProcImp::defineSubst(V3DefineRef* refp) {
if (*cp=='"') quote=!quote;
if (*cp) token += *cp;
}
if (refp->args().size() > numArgs) {
if (refp->args().size() > numArgs
// `define X() is ok to call with nothing
&& !(refp->args().size()==1 && numArgs==0 && trimWhitespace(refp->args()[0],false)=="")) {
fileline()->v3error("Define passed too many arguments: "+refp->name()+"\n");
return " `"+refp->name()+" ";
}

1
src/verilog.l
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@ -864,6 +864,7 @@ escid \\[^ \t\f\r\n]+
"`celldefine" { PARSEP->inCellDefine(true); }
"`default_decay_time"{ws}+[^\n\r]* { } // Verilog spec - delays only
"`default_nettype"{ws}+[a-zA-Z0-9]* { yyerrorf("Unsupported: Verilog 2001 directive not implemented: %s",yytext); } // Verilog 2001
"`default_trireg_strength"{ws}+[^\n\r]* { yyerrorf("Unsupported: Verilog optional directive not implemented: %s",yytext); }
"`delay_mode_distributed" { } // Verilog spec - delays only
"`delay_mode_path" { } // Verilog spec - delays only
"`delay_mode_unit" { } // Verilog spec - delays only