diff --git a/Changes b/Changes
index 04f059847..97e3937e2 100644
--- a/Changes
+++ b/Changes
@@ -11,6 +11,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 **** Fix make uninstall, bug216.  [Iztok Jeras]
 
+**** Fix parametrized defines with empty arguments.
+
 * Verilator 3.800 2010/02/07
 
 Application visible changes:
diff --git a/src/V3PreProc.cpp b/src/V3PreProc.cpp
index 3cd3408f6..192c128fb 100644
--- a/src/V3PreProc.cpp
+++ b/src/V3PreProc.cpp
@@ -511,7 +511,9 @@ string V3PreProcImp::defineSubst(V3DefineRef* refp) {
 	    if (*cp=='"') quote=!quote;
 	    if (*cp) token += *cp;
 	}
-	if (refp->args().size() > numArgs) {
+	if (refp->args().size() > numArgs
+	    // `define X() is ok to call with nothing
+	    && !(refp->args().size()==1 && numArgs==0 && trimWhitespace(refp->args()[0],false)=="")) {
 	    fileline()->v3error("Define passed too many arguments: "+refp->name()+"\n");
 	    return " `"+refp->name()+" ";
 	}
diff --git a/src/verilog.l b/src/verilog.l
index 3f34ad786..9d9a4b596 100644
--- a/src/verilog.l
+++ b/src/verilog.l
@@ -864,6 +864,7 @@ escid	\\[^ \t\f\r\n]+
   "`celldefine"				{ PARSEP->inCellDefine(true); }
   "`default_decay_time"{ws}+[^\n\r]*	{ } // Verilog spec - delays only
   "`default_nettype"{ws}+[a-zA-Z0-9]*	{ yyerrorf("Unsupported: Verilog 2001 directive not implemented: %s",yytext); } // Verilog 2001
+  "`default_trireg_strength"{ws}+[^\n\r]*	{ yyerrorf("Unsupported: Verilog optional directive not implemented: %s",yytext); }
   "`delay_mode_distributed"		{ } // Verilog spec - delays only
   "`delay_mode_path"			{ } // Verilog spec - delays only
   "`delay_mode_unit"			{ } // Verilog spec - delays only